Re: [casper] Used to operate the ROACH2 operating system

Hi, Wang,I noticed that it looks like the "rootserver" IP address returned by DHCP is actually the same as the ROACH2’s IP address (192.168.100.1). I would have expected the "rootserver" IP address to be the same as "bootserver" (192.168.100.100).If you can connect the ROACH2 to the DHCP server

Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

The RFSoC 2x2 sounds intriguing. It will be interesting to see all its capabilities (e.g. will it have high speed networking or other digital I/O?). I enjoyed the web site's positive spin on the conference's virtual nature: "Breakfast is available daily in the kitchen. Menu may vary by

Re: [casper] Issue compiling design from previous version.

I wish I could make all my software work just by wanting it to fail! :) Cheers, Dave > On Feb 2, 2021, at 12:27, Guillermo Gancio wrote: > > Hi Adam, > > Thanks for you answer, and as Murphy said, if it can fail, it > willbut in this case it didn't fail... > I was preparing the files from

Re: [casper] New setup installation problems (python setup.py egg_info" failed with error code 1)

Wow, thanks for these truly awesome forensics, Adam! It sounds like you went down a rabbit hole and lived to tell the tale. I'm sure many of us will benefit from these details. Sorry if this is a FAQ, but what are the prospects for moving the tool flow beyond Ubuntu 16.04? That release is

[casper] Happy New Year!

Happy New Year to the CASPER community!!! It's hard to imagine 2021 not being better than 2020... :P Here's some intriguing AMD/Xilinx news for you: https://hothardware.com/news/amd-patent-hybrid-cpu-fpga-design-xilinx

Re: [casper] Hashpipe_databuf_* control functions semctl/semop errors.

ue Dec 15 17:37:19 2020 : Error (hpguppi_atasnap_pkt_to_FTP_transpose): > error waiting for input buffer, rv: -2 [Invalid argument] That said, there was a bug fix made to the hget.c file last April in commit 75a9a17: https://github.com/david-macmahon/hashpipe/commit/75a9a17b52b265e8caf39

Re: [casper] Hashpipe_databuf_* control functions semctl/semop errors.

Hi, Ross, > On Dec 16, 2020, at 22:08, Ross Andrew Donnachie > wrote: > > Been working on a hashpipe with a pipeline of network, transposition and then > disk-dump threads. We have 24 data-buffers that we rotate through. > > An inconsistent (happens after various amounts of time) crash

Re: [casper] Dropped packets during HASHPIPE data acquisition

Hi, Mark, Glad to hear that your segfault issue has gone away :) even though it sounds frustrating not to understand why :(. Here are some additional responses for you: > On Dec 15, 2020, at 21:00, Mark Ruzindana wrote: > > I'm taking note of the following change for documentation purposes.

Re: [casper] Multi-instance hashpipe "pktsock" on single interface

Hi, Wael, I think I know what's going on here. You don't say how the reported data rate differed from expected, but I suspect the reported data rate was higher than expected. Packet sockets are a low level packet delivery mechanism supported by the kernel. It allows the kernel to copy

Re: [casper] Dropped packets during HASHPIPE data acquisition

Hi, Mark, Sorry to hear you're still getting a segfault. It sounds like you made some progress with gdb, but the fact that you ended up with a different sort of error suggests that you were starting hashpipe in the debugger. To debug your initial segfault problem, you can run hashpipe

Re: [casper] ROACH 2 10 GbE Troubleshooting

Thanks for sharing, Ben! It's not easy to acknowledge solving "silly" problems of one's own making, but it is very valuable/helpful to have these explained on the mailing list. Things like this are far more common than one would perhaps care to admit, especially among more experienced CASPER

Re: [casper] NIC tuning and IRQ binding : Regarding

Hi, Hari, I think modern Linux network drivers use a "polling" approach rather than an interrupt driven approach, so I've found IRQ affinity to be less important than it used to be. This can be observed as relatively low interrupt counts in /proc/interrupts. The main things that I've found

Re: [casper] Help with timing constraint

Hi, Heystek, I think the build will generate a timing report in a file that ends with ".twr". If it's not, you can generate one using the "trce" utility (part of ISE). This will tell you how many nets failed timing and show details of the N worst offenders (I think N defaults to 3 or maybe

Re: [casper] SNAP FPGA data endianness and networking

most of our data is 8- (or 10-) bit anyway so byte order makes little > difference. > > Regards, > James > > > On Tue, Aug 18, 2020 at 3:30 PM David MacMahon <mailto:dav...@berkeley.edu>> wrote: > I guess I’m going to play angels’s advocate and suggest

Re: [casper] SNAP FPGA data endianness and networking

I guess I’m going to play angels’s advocate and suggest the pragmatic over the dogmatic. :) Some standards mandate network byte order, aka big endian, but if you’re not constrained in that way and you know that the data will be processed downstream by a little-endian system for the foreseeable

Re: [casper] Installation of Matlab 2012B

The consistent albeit cryptic names like “enp0s5” might make life easier for automating Linux installations, but I don’t think they make life easier for sysadmins or power users. Fortunately, this naming scheme is optional and it’s easy to switch to the more human-friendly names by adding

Re: [casper] A bug in the Xilinx FFT frame sync

Hi, Sean, Thanks for sharing that link to the interesting (though not overly helpful :P) Xilinx support issue. One thing that might work for you in the meantime (while waiting for CASPER support of 2020.1) is to use 2020.1 to build an FFT-only model and generate it to a netlist (maybe now

Re: [casper] Dropped packets during HASHPIPE data acquisition

ven what I'm > doing before that memcpy(). I will let you know what else I find. > > Thanks again, I really appreciate the help. > > Mark > > On Mon, May 25, 2020 at 4:30 PM David MacMahon <mailto:dav...@berkeley.edu>> wrote: > Hi, Mark, > > Sounds like

Re: [casper] Dropped packets during HASHPIPE data acquisition

Hi, Mark, Sounds like progress! > On May 25, 2020, at 13:56, Mark Ruzindana wrote: > > I have been able to capture data with the first round of frames of the > circular buffer i.e. if I have 160 frames, I am able to capture packets of > frames 0 to 159 at which point right at the memcpy() in

Re: [casper] Dropped packets during HASHPIPE data acquisition

lso very helpful. I'll make sure that the architecture > is as optimal as it should be. > > Thanks again! This was very helpful and I'll update you with the progress > that I make. > > Mark > > > > > On Tue, Mar 31, 2020 at 4:38 PM David MacMahon <m

Re: [casper] Red Pitaya Tutorial 1 reg

Hi, Aravind, > On Apr 2, 2020, at 17:19, Aravind Venkitasubramony > wrote: > > am stuck on the secure copy step mentioned in the tutorial 1 - "As per the > previous figure, navigate to the outputs folder and (secure)copy this across > to a test folder on the workshop server. Instructions to

Re: [casper] Dropped packets during HASHPIPE data acquisition

Just to expand on John's excellent tips, Hashpipe does lock its shared memory buffers with mlock. These buffers will have the NUMA node affinity of the thread that created them so be sure to pin the threads to the desired core or cores by preceding the thread names on the command line with a

Re: [casper] Dropped packets during HASHPIPE data acquisition

Hi, Mark, That packet rate should be very manageable. Are you using the standard "socket()" and "recv()" functions or are you using packet sockets? Packet sockets are a more efficient way to get packets from the kernel that bypasses the kernel's IP stack. It's not as efficient as IBVerbs or

Re: [casper] Use of xBlock for block scripting

I could be wrong, but as I recall, the block diagrams created via xBlocks were (at least at the time) not very conducive to visualizing the structure of the diagrams (e.g. lots of lines/traces overlaid on top of each other). This was not a serious problem when everything worked as it should,

Re: [casper] ROACH Network is unreachable

55.0 > > But can not start the network. > if I run dhclient and can get IP address. > > >> -Original Messages- >> From: "David MacMahon" >> Sent Time: 2019-06-20 22:26:41 (Thursday) >> To: casper@lists.berkeley.edu >> Cc: "

Re: [casper] ROACH Network is unreachable

To further Marc’s query: when you mmcboot into the broken system, what are the contents of /etc/network/interfaces? Dave > On Jun 20, 2019, at 04:06, Marc wrote: > >> On 6/20/19, zhang laiyu wrote: >> Hi，Marc, Jack >>I make some progress but it was not solved. >>I boot the ROACH by

Re: [casper] Data-Width Conversion in FIFO

I thought that system generator included a FIFO block with different input output widths. As I recall, the only tricky parts were ensuring that the overall input/output throughputs are commensurate (true for any FIFO, really) and, for cases with input 2x wider than output, ensuring that the

Re: [casper] adc16x250-8 duplicated samples

th my compilation tools, > but I haven't found the script that performs the data acquisition to the pc. > Does such script exists? > > Thanks, > > Franco > > On Wed, Apr 3, 2019 at 4:52 PM David MacMahon <mailto:dav...@berkeley.edu>> wrote: > Does this symp

Re: [casper] adc16x250-8 duplicated samples

t; <https://my.pcloud.com/publink/show?code=XZMRx67Zpj7XjnkE5PypVuuDCB9Mhu8IJJ37> > > According to an ex-coworker, this is the expected behavior of the adc16x250-8 > board in 16 input mode, because of some constraints in the communication > between the ADC and the FPGA, the FPGA must r

Re: [casper] adc16x250-8 duplicated samples

can get peace of mind :)? > > Some info of my test: > - Board: ROACH2-rev2 > - ADC: ADC16x250-8 coax rev2 > - ADC mode: 16 inputs (demux 1, using David Macmahon initalization code) > - User IP Clock Rate: 140 MHz > - Actual clock frequency used in the adc board: 140MHz

Re: [EXTERNAL] [casper] seeking high accuracy GPS disciplined time/frequency standards ?

Hi, Dan, Thanks for summarizing all the great suggestions from the collective wisdom of the CASPER mailing list! I think getting super precise wrt some external time reference between multiple observatories is an admirable goal, but I think it's also important to keep the ultimate goal in

Re: [casper] Timestamp in ROACH2 and PTP

Hi, Franco, > On Mar 11, 2019, at 07:37, Franco wrote: > > why you call "ARM" the signal/register that resets the time-tracking counter? One of the many definitions of the verb “to arm” is... to equip or prepare for any specific purpose or effective use: to arm a security system; to arm

Re: [casper] ROACH2 10GbE Multicasting

Hi, Luke, I have not used a ROACH2 to send multicast packets, but the MeerKAT folks certainly have. My understanding is that the 10 GbE block does the proper mapping of multicast destination IP address to multicast destination MAC address so it should "just work". I recommend starting with a

Re: [casper] 10 GBE Network Slowdown with Ubuntu 18.04

connected to? FWIW, the Hashpipe program includes a script (hashpipe_topology.sh) that will summarize the NUMA topology of a system vis a vis network cards and/or GPUs. https://github.com/david-macmahon/hashpipe/blob/master/src/hashpipe_topology.sh HTH, Dave > On Oct 3, 2018, at 14:22, Gary,

Re: [casper] Inverse of fft_wideband_real

Hi, Jonathan, The biplex FFT has two complex inputs and two complex outputs. The two input signals are presented "in parallel" (i.e. simultaneously) one sample per input per FPGA cycle, but the output spectra appear serially (i.e. one signal's spectrum followed by the other signal's spectrum)

Re: [casper] Problem when programming ROACH2

Just to add some more details to the problems seen at NRAO, it turns out that some of the uBoot settings passed a "mem=" command line option to the Linux kernel, where was actually greater than the amount of RAM available. It seems that the memory allocator would not reclaim the

Re: [casper] New Wideband Spectrometer Designs

Hi, John, I was speaking with Homin last week at the CASPER Hardware Porting Workshop hosted in Cape Town. He mentioned the Analog Devices 10 Gsps 12-bit ADC that I think is the same one Dan referenced. My recollection of our conversation was that the pricing was not so bad, but I could be

Re: [casper] Programming the SNAP board via the 10GbE interface.

Hi, Jake, I think the problem might be that your DHCP server if offering a 169.254.x.y address. This address range is reserved for “auto-config” IPs so the LWIP code on the microblaze might be refusing to use it. I suspect that it is then timing out and inventing its own auto-config IP

Re: [casper] Problem with ROACH2 netboot

Hi, Bela, I'm not sure what the problem is, but I can offer a few comments that might be helpful... > On May 8, 2018, at 22:50, Bela Dixit wrote: > > U-Boot 2011.06-rc2-0-gd422dc0-dirty (Nov 08 2012 - 16:04:14) > > CPU: AMCC PowerPC 440EPx Rev. A at 533.333 MHz

Re: [casper] temporary ROACH2 faults after power dips and spikes

Hi, Jonathan, The ROACH2s at GB output over all 8 SFP+ ports very often without problem. Not sure whether this matters, but they are connected via fiber optic transceivers rather than copper cables. HTH, Dave > On Apr 19, 2018, at 11:00, Jonathan Weintroub >

Re: [casper] Black box compilation error using Casper XPS flow

ingle clock and a clock > enable. > And the config file was generated from the wizard. > I am attaching herewith my model which is a simple one to generate a sinusoid > signal. > > I would be much grateful if you could please have look at this. > > Thanks, > Vijay. >

Re: [casper] Black box compilation error using Casper XPS flow

> > Thanks for your help on this. > > Regards, > Vijay. > > On Sun, Apr 1, 2018 at 3:34 PM, David MacMahon <dav...@berkeley.edu > <mailto:dav...@berkeley.edu>> wrote: > Hi, Vijay, > > Are you able to compile a simple model without using the back box bloc

Re: [casper] Black box compilation error using Casper XPS flow

Hi, Vijay, Are you able to compile a simple model without using the back box block? The "Possible deprecated use of get on a Java object with an HG Property 'UserData'" waning seems like a simulink and/or system generator issue. And the segmentation fault when running xps is not a good sign

Re: [casper] packets lost of a packetized correlator

in the model, it will be the first thing for > me to check. > > best > homin > > > > On Tue, Mar 13, 2018 at 12:42 PM, David MacMahon <dav...@berkeley.edu > <mailto:dav...@berkeley.edu>> wrote: > Hi, Homin, > > The first thing to do is figure out whe

Re: [casper] packets lost of a packetized correlator

Hi, Homin, The first thing to do is figure out where packet loss is actually happening. The fact that you have to reset the 10G yellow blocks to get things going again suggests that the X engines are not keeping up with the data rate (since the F engines will happily churn out 8.96 Gbps data

Re: [casper] FFT biplex_core block

On Wed, Feb 21, 2018, 10:50 PM David MacMahon <dav...@berkeley.edu> wrote: >> Hi, Jack, >> >> I haven’t used the biplex_core block in a while, but I believe the inputs, >> pol1 and pol2, are two independent complex input signals. The outputs, out1 >> and out2

Re: [casper] FFT biplex_core block

Hi, Jack, I haven’t used the biplex_core block in a while, but I believe the inputs, pol1 and pol2, are two independent complex input signals. The outputs, out1 and out2, first output the frequency channels for input pol1, with the low half of the band being output in bit reversed order on

Re: [casper] sharing CASPER equipment

To further John's comments, Breakthrough Listen has a completely separate set of HPC servers installed at Green Bank that are connected to the same Ethernet switch as the ROACH2s and the VEGAS spectrometer's HPC servers. When using the BL backend, up to 4 of the 8 ROACH2s are configured to

Re: [casper] adc5g Compilation Frequencies

Hi, Franco, I'm not extensively familiar with the inner workings of the AGC5G yellow block, but I suspect the limitation is caused by the somewhat obscure constraints imposed by the MMCM in the Virtex 6. This limitation also affects the ADC16 yellow block. More details can be found here:

Re: [casper] Bof files

Maybe "./mkbof" instead of just "mkbof"? Dave > On Aug 31, 2017, at 23:50, Heystek Grobler wrote: > > Hi Michael > > If I run mkbof -o system.bof –s core_info.tab -t 3 system.bit it gives the > following error/message > > -bash: mkbof: command not found > > I run

Re: [casper] Re: FFT Nyquist Freq

Hi, Andrew, It's been a while since I've looked at the CASPER FFT implementation, but my understanding is that the "real" N-channel FFT actually packs two real FFTs into one 2N-channel complex FFT. Corresponding positive and negative bins of the complex FFT's output are added/subtracted to

Re: [casper] sync_gen parameters questions

Hi, Franco, Maybe CASPER Memo 26 will provide some relevant background info: http://casper.berkeley.edu/memos/sync_memo_v1.pdf HTH, Dave > On Apr 27, 2017, at 07:22, Franco wrote: > > Dear Casper Community, > > >

Re: [casper] RE: ten_Gbe_v2 usage

You may also have to enable "jumbo packets" on any switches between the roach2 and your computer. The default "maximum transmission unit" (MTU) for Ethernet is 1500. Most implementations start with that value by default, but virtually all can be configured to be larger. I'm not sure what the

Re: [casper] Roach2 Tutorial 4 Troubles (Can't Compile .slx or Upload .fpg)

Hi, Alec, I suspect your MLIB_DEVEL_PATH environment variable is not getting set. This error message... > An error or warning occurred during a callback while saving > '/casper_library/casper_library_bus.slx'. …shows that matlab is trying to save the casper_library_bus.slx file in

Re: [casper] High noise floor

Hi, Paulina, That spectrum has way too much structure in it. Something is not working right. I'm not that familiar with tut3, but if there is a way to get a snapshot of samples from the ADC it would be good to verify whether the data from the ADC looks reasonable. Like most systems, the PFB

Re: [casper] Programming a ROACH2

st object was successfully created, then you get this error because it > tries to close the connection before exiting. > > Jason > > On 11 Oct 2016, at 16:09, David MacMahon <dav...@berkeley.edu> wrote: > >> >>> On Oct 11, 2016, at 06:46, Heystek Grobler &l

Re: [casper] Programming a ROACH2

> On Oct 11, 2016, at 06:46, Heystek Grobler wrote: > > Connecting to server 192.168.33.7 on port 7147... FAILURE DETECTED Editorial comments on error handling in tut3.py aside, I think the fact that "FAILURE DETECTED" follows "Connecting to server…" on the same

Re: [casper] Question about complex_addsub block

sed by > another block in the library? > > Franco > > On 10/03/2016 06:14 PM, David MacMahon wrote: >> Hi, Franco, >> >> I can understand your confusion! This block is very unusual. In all >> fairness, that bock does what it says it will do, but it is

Re: [casper] Question about complex_addsub block

Hi, Franco, I can understand your confusion! This block is very unusual. In all fairness, that bock does what it says it will do, but it is unclear what it’s intended purpose is. I think it really computes "a+(b*)" and "-i(a-(b*))". It does not appear to be used by any other blocks in the

Re: [casper] FFT speed optimizations

> On Sep 23, 2016, at 04:17, Guenter Knittel wrote: > > I guess normally one would do this by going to the Function Block Parameters > and setting > > the latencies accordingly. However, I have made so many manual ad-hoc changes > to the > > Simulink model that

Re: [casper] ADC16x250-8 coax rev 2 noise

Hi, Adam, I haven't looked at the spectral content of a terminated input before so I don’t have any comparative results, but I think the spikes you are seeing are caused by mismatched gains and/or offsets of the ADC’s interleaved cores (I think there are a total of 8 cores, also called

Re: [casper] Help with Xilinx and Simulink

Hi, Heystek, > On Aug 16, 2016, at 8:36 AM, Heystek Grobler wrote: > > Details: > standard exception: XNetlistEngine: > Exception message could not be parsed: > com.xilinx.sysgen.netlist.NetlistInternal: couldn't open first > pass text file at >

Re: [casper] gpu correlator

Hi, Gerry, You could start with this: https://github.com/GPU-correlators/xGPU I don’t think Kate Clark has optimized it yet for the GTX 1080, but it should still work reasonably well. Dave > On Jul 26, 2016, at 4:16 PM, Gerald Harp wrote: > > Hi > > Although this is not

Re: [casper] ROACH status queries

Hi, Eric, It sure sounds like your second BOF file is not being properly clocked. I think even roach1 designs include a built-in register (maybe named "says_clk_counter") for estimating the FPGA clock frequency. The python corr package has a function named something like est_clock_freq() (I'm

Re: [casper] XST options

Hi, Gunter, I think you are looking for the resynth_netlist function found in mlib_devel as the file resynth_netlist.m. I think the comments make it rather self-explanatory, but please let me know (via the mailing list) if it's not quite what you're after. Cheers, Dave > On Jul 7, 2016, at

Re: [casper] Error in Simulating Roach 2 Tutorial 1 .mdl file

Hi, Christopher, I don’t have any insights into working with the ""Scope" blocks other than to switch to the "WaveScope" block. It is much nicer than the Scope block, IMHO. It’s a little different to setup, but I think it’s well worth it! FWIW, I think all the tutorials should be modified to

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

you. > > I think the default mode of the adc16 ruby script assumes that, whatever mode > you're using the ADC in, the external clock provided is at the sample rate. > Though, as Matt added, the ADC supports other dividing options if they're > useful to you and you're willing to r

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

of Electrical and Computer Engineering > University of Akron > >> On Wed, Feb 3, 2016 at 12:38 PM, David MacMahon <dav...@astro.berkeley.edu> >> wrote: >> Hi, Vishwa, >> >> The software installed by following the ADC16 user guide had not been >>

Re: [casper] PlanAhead to a working bof

Hi, Johnathon, > On Feb 3, 2016, at 2:26 AM, Gard, Johnathon D. > wrote: > > There are options in the PlanAhead bitfile generation and I could have those > wrong. This could be very likely. The bitgen options that the CASPER flow uses are in

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

script 'adc16_init.rb' does not identify the > '--demux' parameter. I used the code at > 'git://github.com/david-macmahon/casper_adc16.git'. What can I do to set the > parameter? > > Thank you > > > Sincerely, > > Vishwa Seneviratne > Graduate Student > Dept. o

Re: [casper] Working with demux modes of 'ADC16x250-8 coax rev 2'

; Sincerely, > > Vishwa Seneviratne > Graduate Student > Dept. of Electrical and Computer Engineering > University of Akron > > On Wed, Feb 3, 2016 at 11:28 AM, David MacMahon <dav...@astro.berkeley.edu > <mailto:dav...@astro.berkeley.edu>> wrote: > What does "ad

Re: [casper] Matlab / Xilinx startup error

Hi, Brad, I think the problem is with the “awk” utility. It’s probably something like the tools are running the awk binary from the OS, but it ends up using a shared library from your MATLAB or Xilinx installation (or vice versa) and there is something of a mismatch. I recommend trying to

Re: [casper] FFT woes

Hi, Dan, I think the anecdote you mention happened with older Xilinx tools and an older/ancient mlib_devel version. I could be wrong about this, but I’m not convinced it applies to the current versions of things. Any evidence one way or the other would be most welcome. Cheers, Dave > On

Re: [casper] Multicast on 10 gbe on ROACH-2?

As I think Jack commented, I was remembering an old trick that predated multicast support in the core. > On Nov 5, 2015, at 02:51, Marc Welz wrote: > > Not sure if the arp table is involved in this - the destination mac is > (should be) > generated algorithmically from the

Re: [casper] ADC16x250 SERDES calibration issues

Hi, Danny, If you have its dependencies installed, the adc16_plot_taps.rb script can be useful for showing the deskew stuff. The sync errors seem really strange. What is the ADC clock frequency? Have you tried swapping ADC clock cables between a “good” ROACH2 and a “bad/marginal” ROACH2?

Re: [casper] Problems with ADC captured data.

Hi, Sharat, On Sep 6, 2015, at 11:02 PM, Jack Hickish wrote: > As the code suggests, the error comes because bit 1 of core 3 appears to > never be glitch free, no matter what the delay setting. It's not obvious to > me what could cause this. Just to expand on what Jack said, here are a few

Re: [casper] VHDL black-boxing: basic issue

Thanks for the update, Michael! I'm glad you got it resolved. Dave On Aug 10, 2015, at 5:47 AM, Michael D'Cruze wrote: Hi guys, Just to say that Xilinx came back with a pretty standard response, evidently not reading through my message thoroughly enough. After explaining a second

Re: [casper] VHDL black-boxing: basic issue

Hi, Michael, That sounds very strange. Did you drag-and-drop the black box block into the model from the library or did you right-click it in the library and pick Add to model? Are you sure that the dialog box didn't pop up behind other windows (sometimes happens on Linux with X11)? Does

Re: [casper] Roach2 aux clocking and Bram's

Hi, Vereese, That's a very curious failure mode! It's very interesting that everything worked fine when clocking via iADC, but not when clocking via your mezzanine board (or aux_clk) even though the fabric clock rate was the same. I can think of two possible theories for what's going on

Re: [casper] Roach-2 crashing fix

Hi, Marc, On Jul 28, 2015, at 1:34 AM, Marc Welz wrote: So I confess to relying on third parties for this information, but isn't the board populated with 1Gb RAM after all ? When U-Boot starts up it reports that the system has 512 KB of memory. I assume (uh-oh!) that uboot is detecting

Re: [casper] Call for awesome commits

Thanks, Jack!!! That all sounds awesome!!! Dave On May 29, 2015, at 5:27 PM, Jack Hickish wrote: Howdy, I've just merged a bunch of stuff into the casper-astro repository. I haven't yet merged it into master, but it's the casper-astro-soak-test --

Re: [casper] Roach1 Host name lookup error.

Hi, Brad, On May 27, 2015, at 9:37 AM, Brad Dober wrote: I have no issues with the Roach2 that is also connected to this host computer. No issues meaning that you can tftp the uImage file from the server to the roach2? Does tcpdump/wireshark show any clues vis a vis the ROACH1's attempted

Re: [casper] Roach1 Host name lookup error.

Hi, Brad, On May 27, 2015, at 1:15 PM, Brad Dober wrote: Kernel command line: console=ttyS0,115200 mtdparts=physmap-flash.0:1792k(linux),256k@0x1c(fdt),8192k@0x20(root),54656k@0xa0(usr),256k@0x3f6(env),384k@0x3fa(uboot)fdt_addr=0xfc1c

Re: [casper] Roach1 Host name lookup error.

: roach1-4 RP Option 17, length 33: 192.168.40.1:/srv/roach_boot/etch Brad Dober Ph.D. Candidate Department of Physics and Astronomy University of Pennsylvania Cell: 262-949-4668 On Tue, May 26, 2015 at 7:42 PM, David MacMahon dav...@astro.berkeley.edu wrote: Weird

Re: [casper] Roach1 Host name lookup error.

Are you trying to run the ROACH1 on 1 GbE? ROACH1 is not reliable on 1 GbE. You have to force it to be 100 Mbps. This can be done by using an unmanaged non-gigabit switch (or hub), a managed switch that can force its port for the ROACH1 to be 100 Mbsp only. For direct connect, you'll have

Re: [casper] Roach1 Host name lookup error.

it's worth, I am not using jumbo frames. Brad Dober Ph.D. Candidate Department of Physics and Astronomy University of Pennsylvania Cell: 262-949-4668 On Tue, May 26, 2015 at 7:21 PM, David MacMahon dav...@astro.berkeley.edu wrote: Are you trying to run the ROACH1 on 1 GbE? ROACH1

Re: [casper] Select IO DDR Puzzle

Hi, Rich, What are the frequencies of the various clocks? I think you want the OSERDES CLKDIV to be the same freq as the parallel data's clock. For 6 bit parallel data, you want the freq of the OSERDES CLK to be 6*freq(CLKDIV) in SDR mode and 3*freq(CLKDIV) in DDR mode. I think the same is

Re: [casper] Roach1 not working

Hi, Nishanth, On May 7, 2015, at 8:23 PM, Nishanth Shivashankaran wrote: ENET Speed is 1000 Mbps - FULL duplex connection (EMAC0) I don't know whether this is causing your problem, but I believe the ROACH1 ethernet port is not reliable at 1 Gbps. I think you somehow need to limit it to 100

Re: [casper] Skewed data samples

Hi, Tom, Have you calculated the skewness for some largish number of samples or are you just going by the appearance of the histogram? If the latter, are you sure that the apparent skewness is not due to artifacts from the histogram bin limits vs discrete sample values? If you swap ADCs,

[casper] New CASPER toolflow features for planAhead

I pushed a few changes to the casper-astro mlib_devel repository to make life easier when working with Pblocks and planAhead on CASPER designs. ## casper_create_ppr.sh The casper_create_ppr.sh shell script has been added to the ROACH2 base package (XPS_ROACH2_base). After completing a build

[casper] QDR simulations

Does anyone know whether simulations involving the QDR yellow block are supposed to work? They don't seem to be working for me. Maybe I'm doing something wrong? Thanks, Dave

Re: [casper] Operands to the || and operators must be convertible to logical scalar values

Hi, Charles, Is it when you click OK on a block's mask dialog or when you run update diagram or ??? Maybe you can find additional details in the model_sysgen.log or model_sysgen_warning.log or model_sysgen_error.log files? It would really help to know which block or file is causing this

Re: [casper] unable to run tcpborphserver2 from the command line

Hi, Paul, Probably you are, but just to verify, are you running tcpborphserver2 from the command line as root? It sounds like something changes between boot time and command line time. Are you sure it's the same tcpborphserver2 executable that is getting executed? Are you running additional

Re: [casper] Question About The ADC Clock Frequency

Hi, Peter, On Jan 12, 2015, at 1:11 AM, Peter Niu wrote: In our model, We need ADC clock frequency up to 250Mhz. Our ADC boards are ADC16*250-8.We are using adc16*250-8 yellow block in our model modified based PAPER model .However when I changed the XSG core config/User IP Clock

Re: [casper] Compiler merging SRLs -- Timing performance

Hi, Jack, Are the tools are optimizing for area instead of speed? Are you using Pblocks? I don't know if this is relevant to your situation, but I've run into annoyances when the tools use equivalent register removal to save a few flip-flops but end up causing fan-out/routing issues. That

Re: [casper] Question of chose Correlator Architecture

Hi, Peter, If you have enough ports on the switch then you certainly can configure things to send the packets directly from the ROACHs to the various X boxes. The pre-built PAPER model will support this if properly configured. The one thing to keep in mind is the IP-to-MAC address table in

Re: [casper] ROACH serial connection issues

Hi, Norbert, If you hit any key to stop autoboot when it says Hit any key to stop autoboot, does it in fact stop the autoboot? If so, you could use u-boot's printenv command to see what commands get run as part of autoboot and then try to run them by hand to try to figure out where things go

Re: [casper] NFS setup: TFTP permissions problem

Hi, Michael, In addition to the other suggestions, you should check whether you are running dnsmasq in tftp-secure more. That might impose ownership and/or permission restrictions. See man dnsmasq for more details. Dave On Dec 2, 2014, at 6:07 AM, Michael D'Cruze wrote: Hi everyone I'm

Re: [casper] Question of chose Correlator Architecture

Hi, Peter, On Dec 2, 2014, at 9:34 AM, Peter Niu wrote: Thanks for your reply.Our switch ports are enough,but the Nics on roach is not enough(we only have 4 ports each roach),so if we send packets to x box though switch,we only need 4 10Gbe ports on each roach.that is why we want to use

Re: [casper] How to use the EQ model in PAPER?

Hi, Peter, I created a wiki page describing the EQ settings: https://casper.berkeley.edu/wiki/PAPER_Correlator_EQ For the -1 speed grade FPGAs on the RPACH2, the MMCMs on the ROACH2 cannot be configured in HIGH Bandwidth Mode when the input clock frequency is 250 MHz, so they must run in LOW

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