Re: [casper] "No Blocks" in CASPER DSP blockset

Hi Jason, I distinctly remember this problem but couldn't remember the solution. Digging through old emails I came across this from the esteemed Mark Wagner, hopefully it helps! "In case someone else runs into this... I just had this issue that after 'loading' all the blocksets into Simulink and

[casper] Embedded software position

Hi CASPER friends, I wanted to bring this job posting for an Embedded Software engineer at the quantum computing company I'm working at now, Rigetti Computing. The technology we use has a lot of overlap with radio astronomy

Re: [casper] Netboot for ROACH2 in 2017

Hi Adam, When I needed to update tcpborphserver I just cloned the code for it from the repo (I think it was in the katcp codebase) and compiled it on the Roach. I think I had to remount the filesystem to make it writable but otherwise I remember it being fairly straightforward. Hope this helps,

Re: [casper] ROACH2 won't power on

ce of re-work in that > area (missing pads & traces, small wires from nearby vias, etc). We never > use the soft reset switch on the board, so I just removed all of those > parts and the roach2 board now functions as it should. > > Good luck! > Jason > > > > > On

[casper] ROACH2 won't power on

Hi, Our ROACH2 suddenly failed recently. The symptom is that it won't power on. The green AUX power LED is on and the red FAULT LED is on. Pressing the power button and the reset button does nothing. Looking back at the archives, I see that the standard ROACH2 power supply is known to fail after

Re: [casper] Roach2 Tutorial 4 Troubles (Can't Compile .slx or Upload .fpg)

The broken connections between blocks are causing your problem. Often that happens when the ports on a block change between versions. You will likely have to figure out how to connect them back up (perhaps by looking at how they're connected before you run the casper_update_blocks script. Not sure

Re: [casper] Roach2 Tutorial 4 Troubles (Can't Compile .slx or Upload .fpg)

following error appears: >> >> --> Error evaluating 'OpenFcn' callback of SubSystem block >> 'casper_library/Bus'. -->Undefined function or variable >> 'casper_library_bus'. >> ​So, it looks as though I don't actually have access to the bus library. >> Do you

Re: [casper] Roach2 Tutorial 4 Troubles (Can't Compile .slx or Upload .fpg)

ltiple causes. > Unable to load block diagram 'casper_library_bus' > There is no block named 'casper_library_bus/bus_single_port_ram' > Do you have a recommendation on how to fix this error? > > > Best, > Alec > > On Mon, Nov 7, 2016 at 10:03 PM, G Jones <glenn.c

Re: [casper] Roach2 Tutorial 4 Troubles (Can't Compile .slx or Upload .fpg)

Hi Alec (ccing list for posterity), I don't know if there's a .fpg for tutorial 4 for ROACH 2 but I would assume one must be around somewhere. The error message you're seeing is a bit misleading: 'fpga' is not defined because of an error in setting it up, so the exit_fail function is being

Re: [casper] Roach2 Tutorial 4 Troubles (Can't Compile .slx or Upload .fpg)

ou have to update any casper_XPS library >> blocks, or update the .mdl file in any way before attempting to compile it >> with the casper_xps script in MATLAB? >> >> Best, >> Alec >> >> On Wed, Nov 2, 2016 at 3:29 PM, G Jones <glenn.calt...@gmail.com> w

Re: [casper] Roach2 Tutorial 4 Troubles (Can't Compile .slx or Upload .fpg)

n any way before attempting to compile it > with the casper_xps script in MATLAB? > > Best, > Alec > > On Wed, Nov 2, 2016 at 3:29 PM, G Jones <glenn.calt...@gmail.com> wrote: > >> Hi Alec, >> Your compilation error indicates that running system generator fail

Re: [casper] Roach2 Tutorial 4 Troubles (Can't Compile .slx or Upload .fpg)

Hi Alec, Your compilation error indicates that running system generator failed. You need to look in the directory created with the design name for the system generator logs to see where the error occurred. I can't remember the exact name but dig through the sub directories for .log files and the

Re: [casper] 32 Channel PFB and Wideband Real FFT . . .

Hi Randy, I think the issue is that you are processing 16 samples per FPGA clock for VEGAS (if I remember right), so I expect you'll need to hand craft an FFT out of the FFT direct block and twiddle blocks. It might be easier to use a xilinx block in this case, but I haven't actually looked at

[casper] Looking for iADC for long-term loan

Hi, Does anyone have a pair of iADCs (or other 1GHz ADC ZDOK cards) gathering dust that they wouldn't mind lending me for a small project? Thanks, Glenn

Re: [casper] Trouble getting 10GbE working

Do you have your MTU set high enough to receive the length of packets you are sending? On Feb 17, 2016 10:40 AM, "Michael D'Cruze" < michael.dcr...@postgrad.manchester.ac.uk> wrote: > Dear all, > > > > I’m having a little trouble getting the 10GbE data output working > correctly. I have a

Re: [casper] Unconnected output block warnings when compiling with dac_mkid

Regarding the parallel to serial converter, so far I haven't experienced a need to set the configuration registers on the DAC, so I just deleted that block inside the yellow block and tied the output ports to constants. Obviously not a good solution if you do need the configuration registers. Not

Re: [casper] ROACH2 one_gbe block losing data on reception

AM, Henno Kriel he...@ska.ac.za wrote: Hi Glen, I assume you are running your fabric 125MHz? What is the data rate you are trying to sustain? HK On Mon, Jul 27, 2015 at 10:06 PM, G Jones glenn.calt...@gmail.com wrote: Hi, I'm experimenting with the one_gbe block on ROACH2. So far data

[casper] ROACH2 one_gbe block losing data on reception

Hi, I'm experimenting with the one_gbe block on ROACH2. So far data transmission looks flawless, I can capture all the bytes I send. However, receiving data from a computer seems to result in missing data. My design is very simple, I have rx_ack tied high, and then counters on rx_val and the

[casper] SOLVED: ROACH 2 rebooting spontaneously

Hi, I just received a new ROACH 2 and was starting out by hooking up the USB FTDI port to my Windows 8.1 laptop. I let it install a driver for the FTDI chip and all seemed fine, I could see the uboot prompt etc. However, then the board started rebooting itself every ~ 10 seconds. I suspected a

Re: [casper] Roach1 Host name lookup error.

I ran into this a lot when trying to use the sdcard filesystem. I think the problem is that the filesystem is ext2 or something old like that which is prone to corruption if the system is hard rebooted. My advice is use NFS file system. On May 20, 2015 1:20 PM, Brad Dober do...@sas.upenn.edu

Re: [casper] Roach1 not working

Note that for recursive, you need -R not -r On Fri, May 8, 2015 at 3:55 PM, Nishanth Shivashankaran nshiv...@asu.edu wrote: Hi All, Thanks for the reply. I have the exports set to /home/nfs/roach1/current 192.168.70.0/24(sync,rw,no_root_squash) and it did not work. I changed the

Re: [casper] Skewed data samples

Hi Tom, Wouldn't that just cause extra power in the DC bin? Or do the samples still have zero mean? Glenn On Fri, Apr 24, 2015 at 7:32 PM, Kuiper, Thomas (3266) kui...@jpl.nasa.gov wrote: Does any have an idea what might happen to a PFB if the data samples have a slight skewness towards

Re: [casper] ROACH-2 MSSGE 14.2 toolflow compilation takes too long time.

Check your java heap size setting in MATLAB. The default value is often way too low. Search the mailing list archive for more details. On Apr 7, 2015 2:02 AM, Chaudhari Sandeep C. s...@gmrt.ncra.tifr.res.in wrote: Dear All, I started using ROACH-2 toolflow recently. When I tried to

Re: [casper] One_GbE on R2

Hi Brad, It works the same as the 10 GbE port, so the documentation for that block applies directly. GLenn On Mon, Apr 6, 2015 at 11:19 AM, Brad Dober do...@sas.upenn.edu wrote: Hi Casperites, Sorry to bother you, but I'm wondering if anyone has used the one GbE block/port on the Roach2.

Re: [casper] problems with Valon sythn + ROACHI

Do you have a spectrum analyzer to see how much the output of the Valon changes when locked vs unlocked? Have you tried running the Valon at different output frequencies when locked to see if a lower clock rate makes your design work again? On Mon, Mar 23, 2015 at 1:54 PM, Louis Dartez

Re: [casper] ROACH2 MKID Block and DDR3 DRAM

Hi Jonathon, Are you able to share your state machine that moves data from 10 GbE to DRAM? Sounds useful! Thanks, Glenn On Tue, Mar 10, 2015 at 5:04 PM, Gard, Johnathon D. johnathon.g...@nist.gov wrote: Hello Everyone, Just an update on what I have worked out. Thank you Wesely New for

Re: [casper] Reading ROACH2 FPGA BRAMs on PowerPC

Hi Danny, Have you seen this page on the wiki? https://casper.berkeley.edu/wiki/FPGA_Device_Driver_Memo The example code in the links provided there worked well as a good starting point. Glenn On Mon, Feb 16, 2015 at 10:04 PM, Danny Price dpr...@cfa.harvard.edu wrote: Hi all I'd like to read

Re: [casper] Linux Valon Synthesizer

Make sure you have the right permissions for the port, i.e. do: ls -l /dev/ttyUSB0 and make sure you have permissions. On a lot of systems, the ttyUSB* are in the dialout group, so if you add your username to that group and log out and back in, you should be able to access it. Glenn On Thu, Dec

Re: [casper] Problem about the adc frequency in PAPER model.

Also, at least for many ADC boards that have a PPS input, the signal is connected to a 50 ohm resistor to ground and then goes into a TTL to LVDS converter chip. You mentioned 3 Vpp and 0 V offset, so that sounds like the signal is mostly at -1.5 V and then pulses up to +1.5V. I would suggest a

Re: [casper] examples using complex inputs

Several of the MKID systems use I/Q inputs. There's no real trick, they just go through PFB_FIR real blocks (one for each I and Q) and then into the classic fft block as the real and imag parts of the input data. On Fri, Nov 7, 2014 at 1:57 PM, John Ford jf...@nrao.edu wrote: Hi all. Are there

Re: [casper] wide_band_real fft simulation problem of tut3

When you are simulating, do you have the fftshift set appropriately? A pure sine wave will be the worst case for bit growth and overflow, so you'll want an fftshift of 0x I think. On Nov 2, 2014 2:11 AM, Wang Jinqing jqw...@shao.ac.cn wrote: Hi, I can run the tut3.mdl,but I found the

Re: [casper] i_poco4_1024ch_v010

Hi Rolando, I think that sync period seems OK. Accumulation length is set by the user typically, but the default is probably fine. The one concern is that number is 2^32, so be careful that your sync period register is set up to handle that case. The software registers are 32 bits wide, so it

Re: [casper] bitfile

What happens when you try to startupddump? On Thu, Jul 10, 2014 at 10:20 AM, Rolando Paz flx...@gmail.com wrote: Hi Glenn Griffin helped me understand that the file that I should use is called download.bit and not the original file that was compiled :-) However, now I login via telnet

Re: [casper] bitfile

if you see any of the expected messages. You can then add other xil_printf statements to see what part the program is getting stuck on. Glenn On Thu, Jul 10, 2014 at 10:38 AM, Rolando Paz flx...@gmail.com wrote: Do I must do this in main.c file? 2014-07-10 8:30 GMT-06:00 G Jones glenn.calt

Re: [casper] bitfile

:42 GMT-06:00 G Jones glenn.calt...@gmail.com: I mean wherever you have defined the startudp function. I notice there's already this line in there: xil_printf(UDP pcb instantiated\n\r); If I recall, this message will go to the RS-232 serial port. I suggest watching the output from that port

Re: [casper] PowerPC C code modified to automate the transmission of the shared BRAM / IBOB

Hi Rolando, I think you mentioned that you are able to communicate with the IBOB over ethernet. Is that correct? Can you read and set registers using the UDP interface? If so, then the communication is working and the problem is not the communication itself. Glenn On Fri, Jul 4, 2014 at 9:59

Re: [casper] PowerPC C code modified to automate the transmission of the shared BRAM / IBOB

something wrong, so the main.c does not modify the PowerPC code, and hence is not programmed startudpdum. 2014-07-04 8:04 GMT-06:00 G Jones glenn.calt...@gmail.com: Hi Rolando, I think you mentioned that you are able to communicate with the IBOB over ethernet. Is that correct? Can you read

Re: [casper] PowerPC C code modified to automate the transmission of the shared BRAM / IBOB

. Rolando Paz 2014-07-04 8:39 GMT-06:00 G Jones glenn.calt...@gmail.com: Yeah, somehow it looks like the new main.c you are trying to use is not getting included. Where are you putting the main.c? One thing you can try is instead of putting your new main.c in there, try just deleting

Re: [casper] pfb/fft confusion

You want The PFB to have 2^0 simultaneous inputs, then make one PFB for each stream. On Wed, May 28, 2014 at 2:41 PM, Jay Brady jay_br...@live.com wrote: Hello all, With all of the different pfb/fft blocks, I've gotten a bit confused. Some of the terminology used on the wiki is a bit

Re: [casper] pfb/fft confusion

Yes, i.e. if you set it to 2^2 then it means the PFB processes x0,x1,x2,x3 on the first FPGA clock, then x4,x5,x6,x7 on the second FPGA clock, etc... On Wed, May 28, 2014 at 3:15 PM, Jay Brady jay_br...@live.com wrote: So does simultaneous inputs refer to simultaneous samples (within one fpga

Re: [casper] xst hangs

Did you increase your matlab java heap? Search the mailing list archives, sounds like it could be the culprit. Glenn On Apr 11, 2014 9:31 PM, Matt Strader mstra...@physics.ucsb.edu wrote: Hi all, I have a rather large design I'm trying to compile for Roach2. Compilation never gets past xst

Re: [casper] Problem writing to DRAM, ROACH 1

Hi, I think I ran into similar issues, but I don't remember it being a consistent failure for a given size, just that large transfers were somewhat unreliable. I used code like this: def _load_dram_katcp(self,data,tries=2): while tries 0: try:

Re: [casper] init_poco.py and poco_rx_i8_c256.py // IBOB Correlator

Hi Rolando, My guess is that you are not receiving data packets from the ibob, or if you are, they are not the right size. Did you use wireshark to see if packets are coming in and what they look like? Glenn On Apr 3, 2014 10:20 PM, Rolando Paz flx...@gmail.com wrote: Hi all. I run the command

Re: [casper] init_poco.py and poco_rx_i8_c256.py // IBOB Correlator

wrote: Hi Glenn Indeed, I used wireshark. When I run Init_poco.py i8_c256.config, I get what you see in the attached image. But only that is observed. Rolando Paz 2014-04-04 1:12 GMT-06:00 G Jones glenn.calt...@gmail.com: Hi Rolando, My guess is that you are not receiving data packets

Re: [casper] Casper Workshop June 9 to June 13, 2014, Berkeley

Maybe this would be a good year to try and get together a critical mass of people interested in CASPER based kinetic inductance detector (M)KID readout systems at the workshop. Glenn On Tue, Mar 25, 2014 at 3:33 PM, Dan Werthimer d...@ssl.berkeley.eduwrote: Dear CASPER Collaborators and

Re: [casper] Telnet IBOB

Is this with the udp modification? If i recall that disables the telnet interface. Everything can still be accessed by the udp protocol. Glenn On Mar 15, 2014 7:20 PM, Rolando Paz flx...@gmail.com wrote: Hi all. I have trouble connecting IBOB with TELNET. The IBOB IP address is:

Re: [casper] Telnet IBOB

...@gmail.com wrote: Ok, thank you. I think that, that means I have recompiled the bit file, now with port 7? Rolando Paz 2014-03-15 17:48 GMT-06:00 G Jones glenn.calt...@gmail.com: Sorry, what I mean is you need to edit your init_poco.py script and make it use the udp protocol on port 7 instead

Re: [casper] IP address // IBOB

Hi Rolando, Yes, the IP configuration is done in lwipinit.c which I think is part of the modification in the UDP patch. You can modify it there to whatever you like. Glenn On Tue, Mar 11, 2014 at 12:16 PM, Rolando Paz flx...@gmail.com wrote: Hi all again. I'm trying to understand why when I

Re: [casper] IP address // IBOB

, Rolando Paz flx...@gmail.com wrote: Hi Glenn lwipinit.c has the shown in the image lwipinit_c.png You can tell me what I should change in lwipinit.c to correct the IP address and port? Best Regards Rolando Paz 2014-03-11 10:44 GMT-06:00 G Jones glenn.calt...@gmail.com: Hi Rolando, Yes

Re: [casper] ROACH 1 DRAM

for the input on this problem. Hopefully I'll figure it out eventually. Glenn On Tue, Feb 25, 2014 at 2:43 AM, G Jones glenn.calt...@gmail.com wrote: Hi Marc, Thanks for the reply. I would have expected that selecting the 64 MB chunk with the dram_controller register as described in the DRAM block

Re: [casper] ROACH 1 DRAM

: Corr does this in 1MB chunks for this reason. I suspect a problem in the controller. Glenn, can you access over 256MB from the fabric? Jason On 26 Feb 2014, at 17:13, Marc Welz m...@ska.ac.za wrote: On Tue, Feb 25, 2014 at 7:43 AM, G Jones glenn.calt...@gmail.com wrote: Hi Marc

Re: [casper] ROACH 1 DRAM

Hi, Sorry to repost this. Just curious if anyone has experience using more than 256 MB of FPGA DRAM on the ROACH, in particular through the PPC interface. Thanks, Glenn On Wed, Feb 12, 2014 at 12:44 PM, G Jones glenn.calt...@gmail.com wrote: Hi, I'm using the ROACH 1 DRAM for a lookup table

Re: [casper] ROACH 1 DRAM

...@ska.ac.za wrote: On Mon, Feb 24, 2014 at 7:57 PM, G Jones glenn.calt...@gmail.com wrote: Hi, Sorry to repost this. Just curious if anyone has experience using more than 256 MB of FPGA DRAM on the ROACH, in particular through the PPC interface. The PowerPC's virtual memory subsystem

Re: [casper] ROACH-2 USB Communication Dead?

Be sure you try to press enter a few times... the ROACH won't say anything in general except during bootup since it will be sitting there with a login prompt also I think I remember the default port being the second or third one of the 4 that show up when you plug in the usb cable... On Wed,

Re: [casper] Hi // LWIP

to be saved in MSS file Saved project XMP file Error using == gen_xps_files at 680 Programation files generation failed, EDK compilation probably also failed. What do you think? Best Regards Rolando Paz 2013/12/30 G Jones glenn.calt...@gmail.com Hi Rolando, You just need to drop the LWIP

Re: [casper] Caltech's gtkWaveCapture depreciated on Xilinx 14.5

Hi Antony, I made this a very long time ago and haven't maintained it, unfortunately. I now use the built in WaveScope which is nice. The only problem with it is that it tries to expose ALL signals in your design which can overwhelm it when debugging something like the FFT. In those cases, I make

Re: [casper] On the PFB block- a useful feature that we should have

I think the 'sinc bandwidth' feature you mention already exists; it's the Bin Width Scaling (normal=1) field, at least in the slightly outdated version of the libraries I'm using. On Fri, Dec 13, 2013 at 5:37 PM, Madden, Timothy J. tmad...@aps.anl.govwrote: Folks I have a feature request

[casper] Library must be saved before creating new library links

Hi, When I try to update the FFT (ska-sa F505ED55C8) I'm getting an error in fft_wideband_real/fft_direct/butterfly0_0/twiddle/coeff_gen: Initialization commands cannot be evaluated. -- Library must be saved before creating new library links This is a new one to me. Any ideas what it means? The

Re: [casper] Simple clk divider

Usually people just slice the bit you want off a counter. To select the bit using a software register, just use the software register as the select for a mux. Or use the software register as a bit mask and AND it with the counter, then use the output of a relational == 0 as your divided counter.

[casper] Increasing MATLAB Java heap size reduces stalled XSG builds

Hi, I was having issues with complex ROACH 2 designs stalling out during the XSG synthesis phase of the toolflow, where the machine would sit there for days and not make any progress. Mark Wagner suggested I increase the Java Heap Size, which I did, and knock on wood, things seem to be working

Re: [casper] real sampled fft block for 2 inputs per fpga clock

implementation that gives me 2^11 FFT bins/channels for each polarization (FFT size = 2^12). I’ve written my replies below: On Nov 3, 2013, at 4:48 AM, G Jones glenn.calt...@gmail.com wrote: Hi Louis, Replying to the list for the benefit of others. You have the right idea. The biplex real 2x

Re: [casper] real sampled fft block for 2 inputs per fpga clock

The biplex_real_2x is what you want, and it will do two 'polarizations' at a time. On Nov 2, 2013 10:56 PM, Louis Dartez louisdar...@gmail.com wrote: Hello Mark, Glenn, et al., Does anyone know of any CASPER FFT block that will take as inputs two real sampled values (per ADC input) and

Re: [casper] Ten Gigabit Ethernet Pcores

Is there a compelling reason to remove it? If I recall, this version relies on the non-free Xilinx TGE core underneath. It uses a bit more resources, but is also much more forgiving about spacing between packets etc. I found it nice to use in the past, though I have switched over to the new core

Re: [casper] Problem with fi and test suite

I always just break out the real and imag parts before going to matlab workspace On Oct 3, 2013 4:23 PM, Ross Williamson rwilliam...@astro.caltech.edu wrote: Hi, I'm trying to implement a test suite for a correlator and I'm having serious problems with my understanding of fi. The output of

Re: [casper] system.twx missing

The timing was so bad that it didn't get beyond the mapping stage. Follow the instructions in the error message: Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD so run the $XILINX/settings64.sh and then timingan and use the open design option to open the

Re: [casper] Matlab components for toolflow

-point designer Toolbox, Simulink Fixed-point) or just the Fixed-point designer Toolbox? (I have attached lists of toolboxes in our previous and current installation.) Thanks a lot, Nimish On Tue, Sep 17, 2013 at 7:20 PM, G Jones glenn.calt...@gmail.com wrote: As one data point

Re: [casper] Problem with VACC block

I've done some work on that block and it definitely has some bugs. I suggest making a model with the gavrt vacc block which I made a long time ago and is much more thoroughly tested, and then comparing the behavior to the xblocks version and finding the issues for your particular use case that

Re: [casper] Matlab components for toolflow

As one data point I'm successfully compiling designs w/o the fixed point toolboxes. I haven't tried simulating a large design which is where it's claimed to be needed with busses wider than 53 bits or whatever it is On Sep 17, 2013 7:15 PM, Jonathan Weintroub jweintr...@cfa.harvard.edu wrote: Hi

Re: [casper] progdev fails on roach2

Hi Jason, This problem looks a bit different than the one Paul was seeing (but perhaps is related)... In the case you provided, it looks like tcpborphserver3 may have crashed. There is another ROACH2 programming problem seen which shows the following in the telnet session: ?progdev

Re: [casper] ROACH2 dies on fpga.read(...)

Below is a message I wrote with more about the problems we had at NRAO, which did not make it to the list. By the way, others at NRAO are using a recent version of the repository and have had better luck, but based on your experience I wonder if there is still some subtle issue with marginal

Re: [casper] Fwd: how to stop casper_xps?

Kill matlab :) seriously it's pretty difficult. If it's gotten to the point of running the edk backend, you can try to kill an xst or map or par process, which will then cause the matlab script to say error running the toolflow and return you to the matlab prompt. Glenn On Fri, Jun 14, 2013 at

[casper] MUSIC ADC/DAC 4x interface

Hi, Is anyone using the adc_mkid_4x and dac_mkid_4x interfaces to the MUSIC ADC/DAC board? When I use these blocks I get sporadic bit glitches on both the ADC and DAC most of the time, even though timing comes out fine. Reprogramming the ROACH many times and trying many ADC/DAC clock rates

Re: [casper] 38 PFB's on a virtex-6?

Hi David, Traditionally, the CASPER libraries are much better at processing data many times the rate of the FPGA rather than the other way around. So while your suggestion of reusing multipliers is of course a good one, it's generally not well implemented in the CASPER libraries. You might

Re: [casper] Setting up 10gbe core for ROACH2

H Dale, Do you have a lot of other ARP traffic on the network (from a BEE2 for example?) We ran into an issue where the current implementation of tcpborphserver3 (which does all of the tgtap stuff; there is no separate process for it now) will not send enough ARP requests to populate it's ARP

Re: [casper] Setting up 10gbe core for ROACH2

, but it is the main LAN with a lot of devices on it, so this could be our problem. Thanks, Dale On Fri, Jun 7, 2013 at 1:23 PM, G Jones glenn.calt...@gmail.com wrote: H Dale, Do you have a lot of other ARP traffic on the network (from a BEE2 for example?) We ran into an issue where

Re: [casper] netbooting ROACH2

I think John has the right idea: it looks like your server is serving a ROACH 1 uimage to your ROACH 2. We ran into this at NRAO once before as well, but perhaps the other way around. On Thu, Jun 6, 2013 at 9:51 AM, John Ford jf...@nrao.edu wrote: Hi John, Thanks for the reply. My uImage

[casper] tcpborphserver3 logging with network mounted ROACH II

Hi, We're experiencing some intermittent failures where it appears the FPGA is spontaneously deprogramming on the ROACH II. We'd like to try to track this down by turning on logging in tcpborphserver3. Has anyone done this for a network mounted ROACH II? Should we mount an extra directory as r+w

[casper] r2case_event() in dmesg

Hi, Anyone know why there are a bunch of messages like this in dmesg on a ROACH II: r2case_event(): Got type 11, code 8, value 1 attempting led toggle About to toggle cpu_rdy pin7r2case_event(): Got type 11, code 8, value 0 attempting led toggle About to toggle cpu_rdy pin7r2case_event(): Got

[casper] SOLVED: ROACH 2's suddenly freezing left and right

not sure if the problem is some interaction between the ADC5Gs and this commit, or the clock rate or what. Henno, can you double check the code in this commit and see if you can ascertain where the bug might be? Glenn On Thu, Mar 14, 2013 at 12:00 PM, G Jones glenn.calt...@gmail.com wrote: Hi

Re: [casper] SOLVED: ROACH 2's suddenly freezing left and right

not experienced any issues with these bus accesses. What version of TCPBorphServer are you running? Wes On Fri, Mar 15, 2013 at 3:28 PM, G Jones glenn.calt...@gmail.com wrote: Hi, It should have occurred to me sooner, but I checked through the commit logs for mlib_devel and remembered I had

Re: [casper] SOLVED: ROACH 2's suddenly freezing left and right

sizable design running with these changes, that has many register, shared BRAMs and snap blocks, without issues. You mentioned that the design crashes after a while - could you give me a more precise indication of the time span? Regards Henno On Fri, Mar 15, 2013 at 3:28 PM, G Jones

Re: [casper] Question regarding FFT

Hi Nimish, My suggestion is to add snapshot blocks triggered on the sync pulse directly after the FFT and after the blocks that follow it. You can then look at the signal at each stage and see at which stage that strange behavior is occurring. You can also add a test vector generator that puts in

[casper] ROACH 2's suddenly freezing left and right

Hi, For some unknown reason, boffiles I generate with my toolflow cause ROACH 2's to freeze up after a few minutes (I think related to I/O to software registers and shared BRAMs rather than any specific amount of time). I don't know of any changes I made to my toolflow since the last time I

Re: [casper] ROACH 2's suddenly freezing left and right

Also, I meant to mention, I've checked coreinfo.tab etc and they are identical between the working and non-working bofs. On Thu, Mar 14, 2013 at 12:00 PM, G Jones glenn.calt...@gmail.com wrote: Hi, For some unknown reason, boffiles I generate with my toolflow cause ROACH 2's to freeze up after

[casper] 'have_katcp()' missing from katcp_devel

Hi, I'm forwarding this message on behalf of Ray Creager at NRAO. In addition to this question, he was also noticing that KATCP_FLAG_MORE also disappeared w/o warning. Glenn Original Message Subject: 'have_katcp()' missing from katcp_devel Date: Wed, 13 Mar 2013 16:44:30 -0400

Re: [casper] unable to load my boffiles and to configure my roach2

Hi Wes, Can you elaborate on this MMCM stability problem? Which version of ISE was it fixed in? Thanks, Glenn On Mar 12, 2013 5:40 AM, Wesley New wes...@ska.ac.za wrote: Hi Guy, The current casper_astro_mlib should doesn't support ROACH2 as the ROACH2 changes dont seem to have been pulled

Re: [casper] what should I see?

I think your clock source should be 1 GHz right? Also, your signal generator is set to way too high of a level I think. Start with -40 dBm and increase from there. On Tue, Mar 12, 2013 at 4:10 PM, katherine viviana cortes urbina kattycort...@gmail.com wrote: Dear Casperites, 1.- I compile

Re: [casper] Errors compiling pfb_fir_real

, G Jones glenn.calt...@gmail.com wrote: There was a recent change to the pfb inner workings that makes it incompatible with previous models. Drag a new pfb block into the model and set the parameters to those of thee existing block and it should fix it. On Mar 7, 2013 7:12 PM, Ross Williamson

casper-scm rcs block abandoned?

Hi, I was finally looking into the rcs block to start keeping better track of my designs. I was surprised to find that it's currently broken in ska-sa/mlib_devel because it assumes the presence of the MLIB_ROOT environment variable which was renamed in the cleanup to MLIB_DEVEL_PATH. The init

Re: [casper] casper Digest, Vol 63, Issue 9

I just dumped this info on the wiki on the ROACH 2 page since it seems very useful and didn't appear to be there already. Glenn On Wed, Feb 13, 2013 at 2:21 PM, Alec Rust alec.r...@ska.ac.za wrote: Hi John. Grab the latest versions from https://github.com/ska-sa/roach2_nfs_uboot/. If you

Re: [casper] CASPER 10 GbE yellow block

I think it's just a typo and ten_gbe_v2 == 10_gbe_v2 On Wed, Feb 13, 2013 at 5:47 PM, Nimish Sane nimishs...@gmail.com wrote: Hi Dave and others, I was under the impression that ten_Gbe_v2 was suppose to support ROACH2 as well. At least, its mask supports parameters specific to ROACH2 (such

Re: casper-scm Recent mlib_devel pushes to casper-astro

I think this is a good idea anyway, since the undoing bunch of commits message was to restore iBOB + BEE2. So I think it's natural to have a branch in the library. On Tue, Feb 12, 2013 at 2:35 PM, Jason Manley jasonman...@gmail.com wrote: Sorry Dave! The updates all happened when we updated all

Re: [casper] ADC1X5000-8 correlator question

Hi Ross, One point to clarify, the 5000 refers to the samping rate, not the total bandwidth. So a single ADC1X5000 demux 1:2 will give you 5000 Msps at 4 bits per sample, allowing you to sample signals up to 2.5 GHz bandwidth. With a single board, you'd need to put the board in the mode that

Re: [casper] QDR on ROACH vs ROACH2

I'm pretty sure they're twice as wide to keep up with the increased processing throughput possible with the bigger FPGA. On Tue, Feb 5, 2013 at 3:10 PM, David MacMahon dav...@astro.berkeley.edu wrote: When I place a QDR yellow block in a ROACH model, the data out port is 36 bits wide. In a

[casper] tcpborphserver3 failure in tg.c

Hi, As mentioned previously, we've been noticing failures of tcpborphserver3 at a rate that has become annoying enough to finally track down. We compiled from the github source on the ROACH2 itself with debugging enabled and ran through gdb. The failure results are described below. The problem

Re: [casper] tcpborphserver3 failure in tg.c

The katcp command was: ?tap-start tap0 gbe0 10.17.0.65 6 02:02:0A:11:00:41 On Tue, Jan 29, 2013 at 3:42 PM, G Jones glenn.calt...@gmail.com wrote: Hi, As mentioned previously, we've been noticing failures of tcpborphserver3 at a rate that has become annoying enough to finally track down

Re: [casper] ROACH 2 ARP

, and the 02:02:0A... MAC is this ROACH2 itself. So it seems like it is receiving and interpreting ARPs OK. It's just not sending them itself... Any ideas? Thanks, Glenn On Tue, Dec 18, 2012 at 10:58 AM, G Jones glenn.calt...@gmail.com wrote: Hi, In the last couple of days our ROACH2's have decided

Re: [casper] ROACH 2 ARP

need to increase the number of packets per poling itnerval to count as a burst. I'm just going to disable the burst checking for now. Glenn On Tue, Dec 18, 2012 at 2:08 PM, G Jones glenn.calt...@gmail.com wrote: Well I think I located the problem: in tcpborphserver3/tg.c The main do-while loop

[casper] Access to ROACH 2 10 GbE ARP table from PPC?

Hi, Is it possible to access the ARP table from the PPC on ROACH2? I'd like to see what entries it contains and if possible populate it. Thanks, Glenn

Re: [casper] snapshot block with external trigger

So far, the wordwrite workaround does not appear to be working for me, but I'm still investigating. Glenn On Mon, Dec 10, 2012 at 2:12 PM, Alec Rust alec.r...@ska.ac.za wrote: Dave if the wordwrite workaround works lets stick to that for now. The workaround Marc compiled is not really good for

  1   2   >