On May 8, 2007, at 6:53 PM, al davis wrote:
Now you worry me again. Sounds like EDIF.
There is good and bad in any design. There is good even in the
failures. Most (all??) successes happen because of the
failures.
Most disasters result from repeating failures.
To see places where an
On Tuesday 08 May 2007, John Doty wrote:
Most disasters result from repeating failures.
Of course, if you do it exactly the same every time. For
success, you study why it failed and make appropriate changes.
Throwing out the whole thing is a big waste.
Actually, too see what is wrong with
On May 9, 2007, at 7:27 AM, al davis wrote:
On Tuesday 08 May 2007, John Doty wrote:
Most disasters result from repeating failures.
Of course, if you do it exactly the same every time. For
success, you study why it failed and make appropriate changes.
Throwing out the whole thing is a big
One of the ideas I have been playing with A spin off of my work on
back annotation.
I am finishing off a temporary program backnet which loads and runs a
scheme script at the start to read in a netlist and another to read in
an eco file it builds a page with component and pins from the
On Monday 07 May 2007, Stephen Brickles using shaun wrote:
snip maybe the ability to use the file formats of some
of the comercial eda tools?
I haven't heard anyone mentioning OpenAccess on this forum
yet... How about an OpenAccess module for gEDA ? The ability
to open Cadence schematics
On May 8, 2007, at 9:31 AM, al davis wrote:
The bit about compatibility of file formats is one reason why I
brought up VHDL, the structural subset, a while back. Verilog
would work too, but require a hack to work around the missing
entity/architecture feature.
That's what's making me
On Tuesday 08 May 2007, John Doty wrote:
On May 8, 2007, at 9:31 AM, al davis wrote:
The bit about compatibility of file formats is one reason
why I brought up VHDL, the structural subset, a while back.
Verilog would work too, but require a hack to work around
the missing
On May 8, 2007, at 1:24 PM, al davis wrote:
The problem with Spice is that it is not flexible enough. It
might be flexible enough for you, but lots of people bump
against its problems on a regular basis. That's why there are
others like Spectre, Touchstone, Hyperlynx, Nano-sim, Rice, and
On Tuesday 08 May 2007, John Doty wrote:
Well, then quit throwing rocks at SPICE
You are the only one throwing rocks.
and do something
better.
I'm working on it. I even told you what I am doing now, and
why.
SPICE may be a klunker, but it's better than vapor.
Gnucap is not
John Doty wrote:
On May 8, 2007, at 1:24 PM, al davis wrote:
The problem with Spice is that it is not flexible enough. It
might be flexible enough for you, but lots of people bump
against its problems on a regular basis. That's why there are
others like Spectre, Touchstone, Hyperlynx,
On Tuesday 08 May 2007, Russell Shaw wrote:
Does anyone have a diode and BJT model done in verilog-AMS?
Look here:
http://designers-guide.org/VerilogAMS/
Dan said:
http://mextram.sourceforge.net/
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