Thanks for pointing out the distinction, because it is due to non-memory-interlocking instructions not causing interrupts (or any other indications) when the results are garbled that we needed the memory-interlocking instructions to set locks.
I think the other point we sort of glossed over is that even on a uniprocessor an instruction that conditionally sets a value in memory is a very good thing. The CLI, BNE, MVI sequence to obtain a lock does not guarantee that the byte still contains the desired value when the MVI is executed, because an I/O or external interrupt occurring after the CLI and before the MVI could have given a different task higher priority and so it would be dispatched and possibly change the byte. The Test and Set instruction (and by extension CS and CDS) served a valuable function for interrupt-enabled programming under multi-tasking systems on uniprocessors. As you say, the fact that they were also designed to be memory-interlocking makes them even more valuable on multi-processors. Gary Weinhold Senior Application Architect DATAKINETICS | Data Performance & Optimization Phone: +1.613.523.5500 x216<tel:+1.613.523.5500%20x216> Email: [email protected]<mailto:[email protected]> [http://www.dkl.com/wp-content/uploads/2015/07/dkl_logo.png]<http://www.dkl.com/> Visit us online at www.DKL.com<http://www.dkl.com/> [http://www.dkl.com/wp-content/uploads/2015/08/banner.png]<http://www.dkl.com/mailsig> E-mail Notification: The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system. __________ On 2017-08-01 12:29, David W Noon wrote: On Mon, 31 Jul 2017 22:45:51 -0400, Charles Mills ([email protected]<mailto:[email protected]>) wrote about "Re: Question about CPUs" (in <[email protected]><mailto:[email protected]>): People are confusing single processors with multiple processors. On a single processor, almost all instructions are atomic. The exceptions are the obvious ones like MVCL, which are obviously designed to take an interrupt and resume. Yes, all interruptions are at an instruction boundary, and the IAR is saved and resumed. The term you are groping for here is "memory interlock". This was coined by IBM in regard to the TS instruction in that it imposes a lock on its target byte to prevent any other processor in the SMP configuration from manipulating that byte until its operation is complete. In a uniprocessor system, the memory interlock is redundant. In a multiprocessor system it saves your arse. So, instructions like TS, CS, CSD, etc. are *memory atomic* across SMP configurations, not just non-interruptible.
