I worked on some micro or mini architectures where they solved this by having an instruction "disable interrupts for the next two or three instructions." Effectively let you group any two or three instructions together as atomic. (On a uni-processor.)
Charles -----Original Message----- From: IBM Mainframe Assembler List [mailto:[email protected]] On Behalf Of Dave Wade Sent: Tuesday, August 1, 2017 11:25 PM To: [email protected] Subject: Re: Question about CPUs > -----Original Message----- > From: IBM Mainframe Assembler List [mailto:ASSEMBLER- > [email protected]] On Behalf Of Robin Vowels > Sent: 01 August 2017 01:42 > To: [email protected] > Subject: Re: Question about CPUs > > From: "Gary Weinhold" <[email protected]> > Sent: Tuesday, August 01, 2017 12:16 AM > > > > I think (TS) Test and Set was/is atomic and AFAIK was the earliest > > implemented atomic instruction. > > I think that the entire /360 user instruction set would have been of that > kind. > Whilst all instructions are atomic on S/360 in order to implement semaphores you need to me able to test a bit, and set it if clear ATOMICALLY... Without Test and Set you can't do this as it needed two instructions.... > AFIK there was no provision to suspend any instrction and to resume it > after an interrupt. > The instruction had to be allowed to complete, and the IAR saved, so > that when control was passed back to the interrupted program, the next > instruction was executed. > > > I think it addressed the requirement to allow interruptible code to > > fetch, test, and modify a single byte on a single CPU machine with > integrity. > > An external or I/O interrupt could undermine the integrity of a > > TM, Bx, OI/NI instruction sequence in that environment. > > > Gary Weinhold > > Senior Application Architect > > > --- > This email has been checked for viruses by Avast antivirus software. > https://www.avast.com/antivirus
