Base registers include ARs for address location, but index registers don't. Not that it applies to GET.
L R1,Stuff(R2) won't include AR value in address computation. L R1,Stuff(,R2) will So coding a base reg and not an index register has become a "best practice" even if you're not in AR mode. -----Original Message----- From: IBM Mainframe Assembler List <[email protected]> On Behalf Of Lloyd Fuller Sent: Friday, January 22, 2021 8:38 AM To: [email protected] Subject: Re: Help with EZASMI assembly *** External email: Verify sender before opening attachments or links *** Yes, it will. The instruction format is L R1,disp(I1,B1) so you are still using a base of R0 with an index of R1. Sent from my iPad > On Jan 22, 2021, at 9:32 AM, Janko Kalinic <[email protected]> wrote: > > L 15,24(0) would generate a warning when FLAG(PAGE0) is an option. L > 15,24(1) should not. > >> On Fri, Jan 22, 2021 at 8:21 AM Paul Gilmartin < >> [email protected]> wrote: >> >>> On 2021-01-21, at 19:59:19, Gary Weinhold wrote: >>> >>> There was an assembler warning (and it was considered "bad form" if >>> a programmer used the same construction). >>> >> Why "bad form"? Superstition? Fashion? Legibility of dumps? >> And "was" (twice) rather than "is"? >> >>> On 2021-01-21 9:35 p.m., Paul Gilmartin wrote: >>>> On 2021-01-21, at 19:07:36, Gary Weinhold wrote: >>>>> ... the GET still has a "L 15,24(1)". >> >> -- gil >>
