I agree. But again, (if I understand properly) since there's a clock injection, thus a modification of the SB3, what is this FIFO buffer all about ? I mean, they could as well place the clock inside an SB3 and a I2S output instead. No ?
As I understand from reading commentary on this forum and others having the same contributors, due to the size constraints of the SB/Duet enclosures, there is insufficient room to practically implement a clock and upgraded clock power supply to obtain a clean clock output. Given this, the EA solution is to use a buffer to in effect "decouple" the jitter introduced by the SB/Duet clock from the external clock in the Pace Car. The external clock and SB/Duet clock needs to be synchronized to prevent buffer overun. Supposedly, there is no benefit to upgrading the power supply for the SB/Duet and the coneection between the SB/Duet can be made using Toslink without there being any increase in jitter to the Pace Car output, due to the use of the buffer. As to using spdif output to the dac, it would I imagine introduce some jitter, but it is claimed to be low. The i2s format, if proerly implemented, which it can be on many dacs without too much trouble, would seem to be the ideal. -- SNZ ------------------------------------------------------------------------ SNZ's Profile: http://forums.slimdevices.com/member.php?userid=22232 View this thread: http://forums.slimdevices.com/showthread.php?t=57107 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
