Hi, Dan,
On Mar 4, 2010, at 15:15 , Dan Werthimer wrote:
i don't think there will be a power up divide by four ambiguity if
you only have
one adc board
I think there will be a divide by four ambiguity even for one ADC
board. Assuming the ADC sample clock is synchronous to 1 PPS, there
is no way to tell (without somehow calibrating) which of the four ADC
CLK OUT signals the FPGA will get as its input clock.
For this input...
1 PPS 000001111111111111111...
ADC CLK IN 010101010101010101010...
You will get one of these outputs...
ADC CLK OUT 100001111000011110000...
ADC CLK OUT 111000011110000111100...
ADC CLK OUT 011110000111100001111...
ADC CLK OUT 000111100001111000011...
...but how can you tell which one you've got?
Dave
