> * the latency between the Multiplier and Adder had to be set so that all of > it could be absorbed in the pipeline registers within the DSP48E. Normally > 2/3 for Multiplier and 1 for Adder worked fine. > > It seems that this is not actually needed, adding latency to the Multiplier/s and Adders still results in the Adder being folded into the DSP48E for a simple two-multipliers-into-an-adder design.
A good idea is to try the logic out with a small stand-alone design before adding it to your main design. Compile it and check how timing and resource use changes with different parameter sets. Regards Andrew
