> * the latency between the Multiplier and Adder had to be set so that all of > it could be absorbed in the pipeline registers within the DSP48E. Normally > 2/3 for Multiplier and 1 for Adder worked fine. > > It seems that this is not actually needed, adding latency to the Multiplier/s > and Adders still results in the Adder being folded into the DSP48E for a > simple two-multipliers-into-an-adder design. I don't think it works with a latency of zero though. I usually use a multiplier latency of 2 and adder latency of 1 which should result in registered input and output of the DSP slice. I recall seeing no internal pipelining benefit with more latency.
> A good idea is to try the logic out with a small stand-alone design before > adding it to your main design. Compile it and check how timing and resource > use changes with different parameter sets. Good plan. Jason
