See patch.
We need to do two things to allow the intel e7520 to be used by CAR
boards.
Remove unused variables.
Add a declaration for sdram_initialize().
Signed-off-by: Alexandru Gagniuc <mr.nuke...@gmail.com>
Index: src/northbridge/intel/e7520/raminit.c
===================================================================
--- src/northbridge/intel/e7520/raminit.c (revision 6429)
+++ src/northbridge/intel/e7520/raminit.c (working copy)
@@ -653,7 +653,7 @@
goto out;
- val_err:
+ /* val_err: */
die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
@@ -804,7 +804,6 @@
unsigned int dimm;
unsigned int edge;
int32_t data32;
- uint32_t data32_dram;
uint32_t dcal_data32_0;
uint32_t dcal_data32_1;
uint32_t dcal_data32_2;
@@ -1036,10 +1035,6 @@
uint32_t data32;
uint32_t mode_reg;
uint32_t *iptr;
- volatile unsigned long *iptrv;
- msr_t msr;
- uint32_t scratch;
- uint8_t byte;
uint16_t data16;
static const struct {
uint32_t clkgr[4];
@@ -1091,8 +1086,8 @@
data32 = data32 | (1 << 5); /* temp turn off of ODT */
/* Set gearing, then dram controller mode */
/* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
- for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
- cnt<4;cnt++) {
+ iptr = (uint32_t*)gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr;
+ for(cnt=0; cnt<4; cnt++) {
pci_write_config32(PCI_DEV(0, 0x00, 0), 0xa0+(cnt*4), iptr[cnt]);
}
/* 0x7c DRC */
Index: src/northbridge/intel/e7520/raminit.h
===================================================================
--- src/northbridge/intel/e7520/raminit.h (revision 6429)
+++ src/northbridge/intel/e7520/raminit.h (working copy)
@@ -9,4 +9,12 @@
u16 channel1[DIMM_SOCKETS];
};
+#ifndef __ROMCC__
+#if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO
+void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo);
+#else
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+#endif
+#endif /* ROMCC */
+
#endif /* RAMINIT_H */
--
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