I hope you don't mind my submitting two patches in one email. I'm running out of titles to inspire myself from.
Alex
Converts the Supermicro X6DAI-G to use CAR. Depends on the Intel e7525 CAR patch. Signed-off-by: Alexandru Gagniuc <mr/[email protected]> Index: src/mainboard/supermicro/x6dai_g/Kconfig =================================================================== --- src/mainboard/supermicro/x6dai_g/Kconfig (revision 6429) +++ src/mainboard/supermicro/x6dai_g/Kconfig (working copy) @@ -1,3 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + if BOARD_SUPERMICRO_X6DAI_G config BOARD_SPECIFIC_OPTIONS # dummy @@ -7,7 +27,6 @@ select NORTHBRIDGE_INTEL_E7525 select SOUTHBRIDGE_INTEL_ESB6300 select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE Index: src/mainboard/supermicro/x6dai_g/romstage.c =================================================================== --- src/mainboard/supermicro/x6dai_g/romstage.c (revision 6429) +++ src/mainboard/supermicro/x6dai_g/romstage.c (working copy) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -11,14 +31,12 @@ #include "southbridge/intel/esb6300/early_smbus.c" #include "northbridge/intel/e7525/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" -#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "reset.c" #include "superio/winbond/w83627hf/early_serial.c" #include "northbridge/intel/e7525/memory_initialized.c" -#include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -41,9 +59,8 @@ #include "northbridge/intel/e7525/raminit.c" #include "lib/generic_sdram.c" -#include "arch/x86/lib/stages.c" -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller mch[] = { { @@ -59,9 +76,9 @@ if (bist == 0) { /* Skip this if there was a built in self test failure */ - early_mtrr_init(); + /* MTRR init is now handled in cache_as_ram.inc */ if (memory_initialized()) - skip_romstage(); + return; } w83627hf_set_clksel_48(DUMMY_DEV); @@ -78,22 +95,8 @@ pci_write_config32(dev, 0xe8, 0x00000000); pci_write_config8(dev, 0xf0, 0x00); -#if 0 - display_cpuid_update_microcode(); - print_pci_devices(); -#endif -#if 1 enable_smbus(); -#endif -#if 0 - int i; - for(i = 0; i < 1; i++) - dump_spd_registers(); -#endif + disable_watchdogs(); sdram_initialize(ARRAY_SIZE(mch), mch); -#if 1 - dump_pci_device(PCI_DEV(0, 0x00, 0)); -// dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif } Index: src/mainboard/supermicro/x6dai_g/debug.c =================================================================== --- src/mainboard/supermicro/x6dai_g/debug.c (revision 6429) +++ src/mainboard/supermicro/x6dai_g/debug.c (working copy) @@ -1,5 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <spd.h> +#ifdef DEFINED_BUT_NOT_USED static void print_reg(unsigned char index) { unsigned char data; @@ -278,7 +299,6 @@ print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { - unsigned char byte; if ((i % 16) == 0) { print_debug("\n"); print_debug_hex8(i); @@ -311,7 +331,6 @@ print_debug_hex8(device); for(i = 0; (i < 8) ; i++) { - unsigned char byte; status = smbus_read_byte(device, 2); if (status < 0) { print_debug("bad device: "); @@ -326,3 +345,4 @@ print_debug("\n"); } } +#endif /* DEFINED_BUT_NOT_USED */
Remove unused variables, and add a declaration for sdram_initialize() for the Intel e7525 northbridge. This allows the e7525 to be used in CAR boards. Signed-off-by: Alexandru Gagniuc <[email protected]> Index: src/northbridge/intel/e7525/raminit.c =================================================================== --- src/northbridge/intel/e7525/raminit.c (revision 6429) +++ src/northbridge/intel/e7525/raminit.c (working copy) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -659,7 +660,7 @@ goto out; - val_err: +/* val_err: */ die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: @@ -780,7 +781,6 @@ unsigned int dimm; unsigned int edge; int32_t data32; - uint32_t data32_dram; uint32_t dcal_data32_0; uint32_t dcal_data32_1; uint32_t dcal_data32_2; @@ -1013,10 +1013,6 @@ uint32_t data32; uint32_t mode_reg; uint32_t *iptr; - volatile unsigned long *iptrv; - msr_t msr; - uint32_t scratch; - uint8_t byte; uint16_t data16; static const struct { uint32_t clkgr[4]; @@ -1067,8 +1063,8 @@ data32 = data32 | (1 << 5); /* temp turn off of ODT */ /* Set gearing, then dram controller mode */ /* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */ - for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0; - cnt<4;cnt++) { + iptr = (uint32_t*) gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr; + for(cnt=0; cnt<4; cnt++) { pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]); } /* 0x7c DRC */ Index: src/northbridge/intel/e7525/raminit.h =================================================================== --- src/northbridge/intel/e7525/raminit.h (revision 6429) +++ src/northbridge/intel/e7525/raminit.h (working copy) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef RAMINIT_H #define RAMINIT_H @@ -9,4 +29,12 @@ uint16_t channel1[DIMM_SOCKETS]; }; +#ifndef __ROMCC__ +#if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO +void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo); +#else +void sdram_initialize(int controllers, const struct mem_controller *ctrl); +#endif +#endif /* ROMCC */ + #endif /* RAMINIT_H */
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