Last two, I promise.
CARing for the Supermicro NSC PC8374 Superio
Excluded an unused function from being compiled. This superio is only used by the Dell S1850 Signed-off-by: Alexandru Gagniuc <[email protected]> Index: src/superio/nsc/pc8374/early_init.c =================================================================== --- src/superio/nsc/pc8374/early_init.c (revision 6429) +++ src/superio/nsc/pc8374/early_init.c (working copy) @@ -21,7 +21,7 @@ #include <arch/romcc_io.h> #include "pc8374.h" - +#ifdef __ROMCC__ static void pc8374_enable(u16 iobase, u8 *init) { u8 val, count; @@ -45,7 +45,7 @@ outb(val, iobase + 1); } } - +#endif /* __ROMCC__ */ static void pc8374_enable_dev(device_t dev, u16 iobase) { pnp_set_logical_device(dev);
CARing for the Dell s1850 Signed-off-by: Alexandru Gagniuc <[email protected]> Index: src/mainboard/dell/s1850/s1850_fixups.c =================================================================== --- src/mainboard/dell/s1850/s1850_fixups.c (revision 6429) +++ src/mainboard/dell/s1850/s1850_fixups.c (working copy) @@ -1,12 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/romcc_io.h> -static void mch_reset(void) -{ - return; -} - - - static void mainboard_set_e7520_pll(unsigned bits) { return; Index: src/mainboard/dell/s1850/Kconfig =================================================================== --- src/mainboard/dell/s1850/Kconfig (revision 6429) +++ src/mainboard/dell/s1850/Kconfig (working copy) @@ -1,3 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + if BOARD_DELL_S1850 config BOARD_SPECIFIC_OPTIONS # dummy @@ -8,7 +28,6 @@ select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC8374 - select ROMCC select HAVE_HARD_RESET select HAVE_OPTION_TABLE select BOARD_HAS_HARD_RESET Index: src/mainboard/dell/s1850/watchdog.c =================================================================== --- src/mainboard/dell/s1850/watchdog.c (revision 6429) +++ src/mainboard/dell/s1850/watchdog.c (working copy) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <device/pnp_def.h> #define NSC_WD_DEV PNP_DEV(0x2e, 0xa) @@ -5,9 +25,9 @@ #define ICH5_WDBASE 0x400 #define ICH5_GPIOBASE 0x500 +#if 0 static void disable_sio_watchdog(device_t dev) { -#if 0 /* FIXME move me somewhere more appropriate */ pnp_set_logical_device(dev); pnp_set_enable(dev, 1); @@ -15,8 +35,8 @@ /* disable the sio watchdog */ outb(0, NSC_WDBASE + 0); pnp_set_enable(dev, 0); +} #endif -} static void disable_ich5_watchdog(void) { Index: src/mainboard/dell/s1850/romstage.c =================================================================== --- src/mainboard/dell/s1850/romstage.c (revision 6429) +++ src/mainboard/dell/s1850/romstage.c (working copy) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> @@ -9,7 +29,6 @@ #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc8374/early_init.c" -#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" @@ -17,7 +36,6 @@ // #include "reset.c" #include "s1850_fixups.c" #include "northbridge/intel/e7520/memory_initialized.c" -#include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1) @@ -124,7 +142,6 @@ static inline void bmc_foad(void) { - unsigned char c; /* be safe; make sure it is really ready */ while ((inb(ipmicsr)>>6)) { outb(0x60, ipmicsr); @@ -142,9 +159,7 @@ /* end IPMI garbage */ -#include "arch/x86/lib/stages.c" - -static void main(unsigned long bist) +void main(unsigned long bist) { u8 b; u16 w; @@ -162,7 +177,7 @@ }; /* superio setup */ - /* observed from serialice */ + /* observed from serialice - UNUSED static const u8 earlyinit[] = { 0x21, 0x11, 0x11, 0x22, 1, 1, @@ -170,7 +185,7 @@ 0x24, 0x81, 0x81, 0x26, 0, 0, 0, - }; + };*/ /* using SerialICE, we've seen this basic reset sequence on the dell. * we don't understand it as it uses undocumented registers, but @@ -224,18 +239,6 @@ w = inw(0x866); outw(w|2, 0x866); -#if 0 - /*seriaice shows - dell does this so leave it here so I don't forget - */ - /* SMBUS */ - pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0); - - /* unknown */ - b = inb(0x8c2); - outb(0xdf, 0x8c2); -#endif - /* another device enable? */ b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4); b |= 2; @@ -253,9 +256,9 @@ } if (bist == 0) { /* Skip this if there was a built in self test failure */ - early_mtrr_init(); + /* MTRR init is now handled in cache_as_ram.inc */ if (memory_initialized()) - skip_romstage(); + return; } /* Setup the console */ mainboard_set_ich5(); @@ -292,34 +295,11 @@ pci_write_config32(dev, 0xe8, 0x00000000); pci_write_config8(dev, 0xf0, 0x00); -#if 0 - display_cpuid_update_microcode(); -#endif -#if 1 - print_pci_devices(); -#endif -#if 1 enable_smbus(); -#endif -#if 0 -// dump_spd_registers(&cpu[0]); - int i; - for(i = 0; i < 1; i++) - dump_spd_registers(); -#endif -#if 1 - show_dram_slots(); -#endif + disable_watchdogs(); // dump_ipmi_registers(); mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); -#if 0 - dump_pci_devices(); -#endif -#if 1 - dump_pci_device(PCI_DEV(0, 0x00, 0)); -// dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif } Index: src/mainboard/dell/s1850/debug.c =================================================================== --- src/mainboard/dell/s1850/debug.c (revision 6429) +++ src/mainboard/dell/s1850/debug.c (working copy) @@ -1,5 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <spd.h> +#ifdef DEFINED_BUT_NOT_USED static void print_reg(unsigned char index) { unsigned char data; @@ -215,7 +236,6 @@ print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { - unsigned char byte; if ((i % 16) == 0) { print_debug("\n"); print_debug_hex8(i); @@ -242,7 +262,6 @@ device = DIMM0; while(device <= DIMM7) { int status = 0; - int i; print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); @@ -272,7 +291,6 @@ print_debug_hex8(device); for(i = 0; (i < 8) ; i++) { - unsigned char byte; status = smbus_read_byte(device, 2); if (status < 0) { print_debug("bad device: "); @@ -287,3 +305,4 @@ print_debug("\n"); } } +#endif /* DEFINED_BUT_NOT_USED */ \ No newline at end of file
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