See patch.
Fixes the build errors that occur when compiling the Supermicro X6DHE-G2 as a CAR board.
Unused variables are removed, and unused functions are excluded with #if/#endif Signed-off-by: Alexandru Gagniuc <mr/[email protected]> Index: src/mainboard/supermicro/x6dhe_g2/Kconfig =================================================================== --- src/mainboard/supermicro/x6dhe_g2/Kconfig (revision 6429) +++ src/mainboard/supermicro/x6dhe_g2/Kconfig (working copy) @@ -8,7 +8,6 @@ select SOUTHBRIDGE_INTEL_I82801EX select SOUTHBRIDGE_INTEL_PXHD select SUPERIO_NSC_PC87427 - select ROMCC select HAVE_HARD_RESET select BOARD_HAS_HARD_RESET select HAVE_OPTION_TABLE Index: src/mainboard/supermicro/x6dhe_g2/watchdog.c =================================================================== --- src/mainboard/supermicro/x6dhe_g2/watchdog.c (revision 6429) +++ src/mainboard/supermicro/x6dhe_g2/watchdog.c (working copy) @@ -5,6 +5,7 @@ #define ESB6300_WDBASE 0x400 #define ESB6300_GPIOBASE 0x500 +#ifdef DEFINED_BUT_NOT_USED static void disable_sio_watchdog(device_t dev) { #if 0 @@ -17,7 +18,7 @@ pnp_set_enable(dev, 0); #endif } - +#endif static void disable_esb6300_watchdog(void) { /* FIXME move me somewhere more appropriate */ @@ -46,7 +47,7 @@ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); } - +#ifdef DEFINED_BUT_NOT_USED static void disable_jarell_frb3(void) { #if 0 @@ -88,7 +89,7 @@ outl(value, base + 0x38); #endif } - +#endif static void disable_watchdogs(void) { // disable_sio_watchdog(NSC_WD_DEV); Index: src/mainboard/supermicro/x6dhe_g2/romstage.c =================================================================== --- src/mainboard/supermicro/x6dhe_g2/romstage.c (revision 6429) +++ src/mainboard/supermicro/x6dhe_g2/romstage.c (working copy) @@ -9,14 +9,12 @@ #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" -#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "reset.c" #include "superio/nsc/pc87427/early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" -#include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1) @@ -31,9 +29,7 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -static void mch_reset(void) {} static void mainboard_set_e7520_pll(unsigned bits) {} -static void mainboard_set_e7520_leds(void) {} static inline int spd_read_byte(unsigned device, unsigned address) { @@ -42,9 +38,8 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" -#include "arch/x86/lib/stages.c" -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller mch[] = { { @@ -56,9 +51,9 @@ if (bist == 0) { /* Skip this if there was a built in self test failure */ - early_mtrr_init(); + /* MTRR init is handled as part of cache_as_ram.inc */ if (memory_initialized()) - skip_romstage(); + return; } /* Setup the console */ @@ -98,11 +93,4 @@ // dump_ipmi_registers(); // mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); -#if 0 - dump_pci_devices(); -#endif -#if 1 - dump_pci_device(PCI_DEV(0, 0x00, 0)); - //dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif } Index: src/mainboard/supermicro/x6dhe_g2/debug.c =================================================================== --- src/mainboard/supermicro/x6dhe_g2/debug.c (revision 6429) +++ src/mainboard/supermicro/x6dhe_g2/debug.c (working copy) @@ -1,5 +1,5 @@ #include <spd.h> - +#ifdef DEFINED_BUT_NOT_USED static void print_reg(unsigned char index) { unsigned char data; @@ -137,27 +137,7 @@ } } -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\n"); - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\n"); - } - } -} - static void dump_bar14(unsigned dev) { int i; @@ -202,7 +182,7 @@ dump_pci_device(dev); } } - +#endif #if 0 static void dump_spd_registers(const struct mem_controller *ctrl) { @@ -264,7 +244,6 @@ } } } -#endif void dump_spd_registers(void) { @@ -278,7 +257,6 @@ print_debug_hex8(device); for(i = 0; (i < 256) ; i++) { - unsigned char byte; if ((i % 16) == 0) { print_debug("\n"); print_debug_hex8(i); @@ -311,7 +289,6 @@ print_debug_hex8(device); for(i = 0; (i < 8) ; i++) { - unsigned char byte; status = smbus_read_byte(device, 2); if (status < 0) { print_debug("bad device: "); @@ -326,3 +303,4 @@ print_debug("\n"); } } +#endif \ No newline at end of file
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
