On Thursday 22 January 2009, Kevin Hilman wrote: > Here's a another pass at better modeling of clocks and PLLs. The > longer term goal being the ability model the clock tree well enough to > do DVFS on parts that support it.
I didn't try running it, but I did a quick skim ... looks like a good approach. The <chip>.c files are good to see. - Dave > > - generalize PLLs > - model PLLs, their dividers and the resulting SYSCLKs > - add concept of clock parents > - drop 'div_by_*' in favor of using PLL dividers > - misc. other minor cleanups > - move clock definitions into chip-specific code > - start using clk_get_rate() to get rates (UART, timers) > > TODO: > - implement the programmable dividers > - seek-and-destroy hardcoded clock rates > > Signed-off-by: Kevin Hilman <[email protected]> _______________________________________________ Davinci-linux-open-source mailing list [email protected] http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
