> > Another suggestion: have clock nodes for all the PLL taps,
> > instead of eliding the divide-by-one taps and the ones that
> > only feed one module. For consistency and clarity.
>
> Not sure I follow the suggestion here...
>
> So for example, on dm355 are you suggesting I add pll1_sysclk3 and
> pll1_sysclk4 nodes instead of the vpbe and vpss nodes, or have
> the single peripheral nodes as children of the sysclks?
The latter, like you do below.
... Although with these two clocks there's a separate issue related
to confusing docs about VPSS clocking. Yes, pll1_syscl4 feeds VPSS,
but there are two LPSC gates for VPSS clocks (master and slave) that
are shared between VPFE and VPBE, plus a DAC clock off pll1_sysclk3.
Presumably that confusion will get sorted when drivers for all that
get merged. I didn't explore this issue; there might even be issues
specific to a given SoC.
- Dave
> Something like this: ?
>
> static struct clk pll1_sysclk3 = {
> .name = "pll1_sysclk3",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV3,
> };
>
> static struct clk pll1_sysclk4 = {
> .name = "pll1_sysclk4",
> .parent = &pll1_clk,
> .flags = CLK_PLL,
> .div_reg = PLLDIV4,
> };
>
> static struct clk vpbe_clk = {
> .name = "vpbe",
> .parent = &pll1_sysclk3,
> .flags = CLK_PLL,
> };
>
> static struct clk vpss_clk = {
> .name = "vpss",
> .parent = &pll1_sysclk4,
> .flags = CLK_PLL,
> };
>
>
>
> Kevin
>
>
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