Appended: tweaks that make it work on dm355 and
report the correct clocks (except that PLLDIV3 and
PLLDIV4 aren't passed along).
I think the board init code should pass the rate
of the main oscillator into the clock init code.
- Dave
================ CUT HERE
Make this work on DM355 EVM ... add Makefile support, and
fixes including ASoC clock name changes.
Clock updates:
- We can't enable/disable PLL outputs
- Use the spinlock is to protect those refcounts
- Show tree structure
- Parents must be enabled before children, disabled after
- Remove the needless clk->id mechanism
- Bugfix PLL multiplier mask
- Include PSC init
Audit the DM355 clock tree:
- Add entries for timer[0123], MJCP, clkout[123], vpss, vpbe
- Correct parentage ... there is no SYCLK5, just SYSCLK3!
- Comment some remaining missing entries
Problem noted by a quick read of /proc/davinci_clocks: there's no
mechanism to couple the VPBE clock and PLLDIV3; or the VPSS clock
and PLLDIV4. This will need to be addressed before their dividers
can be programmed, too. Probably simplest to let programmable clocks
hold a pointer to the relevant PLLDIV register
---
arch/arm/mach-davinci/Makefile | 4
arch/arm/mach-davinci/board-dm355-evm.c | 2
arch/arm/mach-davinci/clock.c | 147 ++++++++++++++++++-----------
arch/arm/mach-davinci/clock.h | 31 +++---
arch/arm/mach-davinci/dm355.c | 152 +++++++++++++++++++++++++-----
arch/arm/mach-davinci/time.c | 8 -
sound/soc/davinci/davinci-i2s.c | 2
7 files changed, 248 insertions(+), 98 deletions(-)
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -7,6 +7,10 @@
obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
gpio.o devices.o usb.o dma.o common.o iram.o
+obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o
+obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o
+obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o
+
obj-$(CONFIG_DAVINCI_MUX) += mux.o mux_cfg.o
# Board specific
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -235,8 +235,6 @@ static struct spi_board_info dm355_evm_s
static __init void dm355_evm_init(void)
{
- davinci_psc_init();
-
gpio_request(1, "dm9000");
gpio_direction_input(1);
dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1);
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -95,13 +95,10 @@ done:
struct clk *clk_get(struct device *dev, const char *id)
{
struct clk *p, *clk = ERR_PTR(-ENOENT);
- int idno;
struct clk_mapping *mapping;
- if (dev == NULL || dev->bus != &platform_bus_type)
- idno = -1;
- else
- idno = to_platform_device(dev)->id;
+ if (!id)
+ return ERR_PTR(-EINVAL);
mutex_lock(&clocks_mutex);
@@ -118,14 +115,6 @@ struct clk *clk_get(struct device *dev,
}
list_for_each_entry(p, &clocks, node) {
- if (p->id == idno &&
- strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
- clk = p;
- goto found;
- }
- }
-
- list_for_each_entry(p, &clocks, node) {
if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
clk = p;
break;
@@ -135,7 +124,8 @@ struct clk *clk_get(struct device *dev,
found:
mutex_unlock(&clocks_mutex);
- WARN_ON(clk == ERR_PTR(-ENOENT));
+ WARN(IS_ERR(clk), "CLK: can't find %s/%s\n",
+ dev ? dev_name(dev) : "nodev", id);
return clk;
}
EXPORT_SYMBOL(clk_get);
@@ -147,38 +137,35 @@ void clk_put(struct clk *clk)
}
EXPORT_SYMBOL(clk_put);
-static int __clk_enable(struct clk *clk)
+static void __clk_enable(struct clk *clk)
{
- if (clk->flags & ALWAYS_ENABLED)
- return 0;
-
- davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1);
- return 0;
+ if (clk->parent)
+ __clk_enable(clk->parent);
+ if (clk->usecount++ == 0 && !(clk->flags & CLK_PLL))
+ davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1);
}
static void __clk_disable(struct clk *clk)
{
- if (clk->usecount)
- return;
-
- davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0);
+ BUG_ON(clk->usecount == 0);
+ if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
+ davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0);
+ if (clk->parent)
+ __clk_disable(clk->parent);
}
int clk_enable(struct clk *clk)
{
unsigned long flags;
- int ret = 0;
-
+
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
- if (clk->usecount++ == 0) {
- spin_lock_irqsave(&clockfw_lock, flags);
- ret = __clk_enable(clk);
- spin_unlock_irqrestore(&clockfw_lock, flags);
- }
+ spin_lock_irqsave(&clockfw_lock, flags);
+ __clk_enable(clk);
+ spin_unlock_irqrestore(&clockfw_lock, flags);
- return ret;
+ return 0;
}
EXPORT_SYMBOL(clk_enable);
@@ -189,11 +176,9 @@ void clk_disable(struct clk *clk)
if (clk == NULL || IS_ERR(clk))
return;
- if (clk->usecount > 0 && !(--clk->usecount)) {
- spin_lock_irqsave(&clockfw_lock, flags);
- __clk_disable(clk);
- spin_unlock_irqrestore(&clockfw_lock, flags);
- }
+ spin_lock_irqsave(&clockfw_lock, flags);
+ __clk_disable(clk);
+ spin_unlock_irqrestore(&clockfw_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
@@ -230,8 +215,13 @@ int clk_register(struct clk *clk)
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
+ if (WARN(clk->parent && !clk->parent->rate,
+ "CLK: %s parent %s has no rate!\n",
+ clk->name, clk->parent->name))
+ return -EINVAL;
+
mutex_lock(&clocks_mutex);
- list_add(&clk->node, &clocks);
+ list_add_tail(&clk->node, &clocks);
mutex_unlock(&clocks_mutex);
/* If rate passed in, use it */
@@ -270,7 +260,7 @@ static int __init clk_disable_unused(voi
unsigned long flags;
list_for_each_entry(ck, &clocks, node) {
- if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED))
+ if (ck->usecount > 0)
continue;
printk(KERN_INFO "Clocks: disable unused %s\n", ck->name);
@@ -288,29 +278,38 @@ static void __init clk_pll_init(struct c
{
u32 i, ctrl, plldiv, mult = 1, prediv = 1, postdiv = 1;
u8 bypass;
+ struct pll_data *pll = clk->pll_data;
void __iomem *base;
- base = IO_ADDRESS(clk->pll_data->phys_base);
+ base = IO_ADDRESS(pll->phys_base);
ctrl = __raw_readl(base + PLLCTL);
clk->rate = clk->parent->rate;
if (ctrl & PLLCTL_PLLEN) {
bypass = 0;
- mult = __raw_readl(base + PLLM) & PLLM_PLLM_MASK;
- mult += 1;
+ mult = __raw_readl(base + PLLM);
+ mult = (mult & PLLM_PLLM_MASK) + 1;
} else
bypass = 1;
- if (clk->pll_data->flags & PLL_HAS_PREDIV) {
+ if (pll->flags & PLL_HAS_PREDIV) {
prediv = __raw_readl(base + PREDIV);
if (prediv & PLLDIV_EN)
prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
+ else
+ prediv = 1;
}
- if (clk->pll_data->flags & PLL_HAS_POSTDIV) {
+ /* pre-divider is fixed, but (some?) chips won't report that */
+ if (cpu_is_davinci_dm355() && pll->num == 1)
+ prediv = 8;
+
+ if (pll->flags & PLL_HAS_POSTDIV) {
postdiv = __raw_readl(base + POSTDIV);
if (postdiv & PLLDIV_EN)
postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
+ else
+ postdiv = 1;
}
if (!bypass) {
@@ -320,7 +319,7 @@ static void __init clk_pll_init(struct c
}
printk(KERN_INFO "PLL%d: input = %lu MHz [ ",
- clk->pll_data->num, clk->parent->rate / 1000000);
+ pll->num, clk->parent->rate / 1000000);
if (bypass)
printk("bypass ");
if (prediv > 1)
@@ -332,7 +331,7 @@ static void __init clk_pll_init(struct c
printk("] --> %lu MHz output.\n", clk->rate / 1000000);
for (i = 0; i < MAX_PLL_DIVISORS; i++) {
- u32 v, div_reg = clk->pll_data->div_regs[i];
+ u32 v, div_reg = pll->div_regs[i];
plldiv = 0;
if (div_reg) {
@@ -360,15 +359,18 @@ int __init davinci_clk_init(struct clk *
struct clk *clkp;
int i = 0;
+ davinci_psc_init();
while ((clkp = clocks[i++])) {
- clk_register(clkp);
-
if (clkp->pll_data)
clk_pll_init(clkp);
+ clk_register(clkp);
- /* FIXME: is this really needed? why ? */
- /* Turn on clocks that have been force enabled */
- if (clkp->usecount)
+ /* FIXME: remove equivalent special-cased code from
+ * davinci_psc_init() once cpus list *all* clocks.
+ */
+
+ /* Turn on clocks that Linux doesn't otherwise manage */
+ if (clkp->flags & ALWAYS_ENABLED)
clk_enable(clkp);
}
@@ -394,12 +396,47 @@ static void davinci_ck_stop(struct seq_f
{
}
-static int davinci_ck_show(struct seq_file *m, void *v)
+#define CLKNAME_MAX 10 /* longest clock name */
+#define NEST_DELTA 2
+#define NEST_MAX 4
+
+static void
+dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
{
- struct clk *cp;
+ char *state;
+ char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
+ struct clk *clk;
+ unsigned i;
- list_for_each_entry(cp, &clocks, node)
- seq_printf(m, "%s %lu %d\n", cp->name, cp->rate, cp->usecount);
+ state = (parent->flags & CLK_PLL) ? "pll" : "psc";
+
+ /* <nest spaces> name <pad to end> */
+ memset(buf, ' ', sizeof(buf) - 1);
+ buf[sizeof(buf) - 1] = 0;
+ i = strlen(parent->name);
+ memcpy(buf + nest, parent->name,
+ min(i, (unsigned)(sizeof(buf) - 1 - nest)));
+
+ seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
+ buf, parent->usecount, state, clk_get_rate(parent));
+ /* REVISIT show device associations too */
+
+ /* cost is now small, but not linear... */
+ list_for_each_entry(clk, &clocks, node) {
+ if (clk->parent == parent)
+ dump_clock(s, nest + NEST_DELTA, clk);
+ }
+}
+
+static int davinci_ck_show(struct seq_file *m, void *v)
+{
+ /* Show clock tree; we know the main oscillator is first.
+ * We trust nonzero usecounts equate to PSC enables...
+ */
+ mutex_lock(&clocks_mutex);
+ if (!list_empty(&clocks))
+ dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
+ mutex_unlock(&clocks_mutex);
return 0;
}
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -25,7 +25,7 @@
#define PLLCTL_CLKMODE BIT(8)
#define PLLM 0x110
-#define PLLM_PLLM_MASK 0x1f
+#define PLLM_PLLM_MASK 0xff
#define PREDIV 0x114
#define PLLDIV1 0x118
@@ -33,6 +33,13 @@
#define PLLDIV3 0x120
#define POSTDIV 0x128
#define BPDIV 0x12c
+#define PLLCMD 0x138
+#define PLLSTAT 0x13c
+#define PLLALNCTL 0x140
+#define PLLDCHANGE 0x144
+#define PLLCKEN 0x148
+#define PLLCKSTAT 0x14c
+#define PLLSYSTAT 0x150
#define PLLDIV4 0x160
#define PLLDIV5 0x164
#define PLLDIV6 0x168
@@ -56,22 +63,22 @@ struct clk {
struct module *owner;
const char *name;
unsigned long rate;
- int id;
- __s8 usecount;
- __u8 flags;
- __u8 lpsc;
- __u8 fixed_divisor;
+ u8 usecount;
+ u8 flags;
+ u8 lpsc;
+ u8 fixed_divisor;
struct clk *parent;
struct pll_data *pll_data;
};
/* Clock flags */
-#define RATE_CKCTL 1
-#define RATE_FIXED 2
-#define RATE_PROPAGATES 4
-#define VIRTUAL_CLOCK 8
-#define ALWAYS_ENABLED 16
-#define ENABLE_REG_32BIT 32
+//#define RATE_CKCTL 1
+//#define RATE_FIXED 2
+//#define RATE_PROPAGATES 4
+//#define VIRTUAL_CLOCK 8
+#define ALWAYS_ENABLED BIT(4)
+//#define ENABLE_REG_32BIT 32
+#define CLK_PLL BIT(6)
int davinci_clk_associate(struct device *dev, const char *logical_clockname,
const char *physical_clockname);
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -12,74 +12,145 @@
#include <linux/init.h>
#include <linux/clk.h>
-#include <mach/dm644x.h>
+#include <mach/dm355.h>
#include <mach/clock.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include "clock.h"
-#define DM355_REF_FREQ 24000000
+#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
static struct pll_data pll1_data = {
.num = 1,
.phys_base = DAVINCI_PLL1_BASE,
+ .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
.div_regs = {PLLDIV1, PLLDIV2, PLLDIV3, PLLDIV4},
};
static struct pll_data pll2_data = {
.num = 2,
.phys_base = DAVINCI_PLL2_BASE,
+ .flags = PLL_HAS_PREDIV,
.div_regs = {PLLDIV1},
};
static struct clk ref_clk = {
.name = "ref_clk",
+ /* FIXME -- crystal rate is board-specific */
.rate = DM355_REF_FREQ,
- .flags = ALWAYS_ENABLED,
+ .flags = CLK_PLL,
};
static struct clk pll1_clk = {
.name = "pll1",
.parent = &ref_clk,
+ .flags = CLK_PLL,
.pll_data = &pll1_data,
};
static struct clk pll2_clk = {
.name = "pll2",
.parent = &ref_clk,
+ .flags = CLK_PLL,
.pll_data = &pll2_data,
};
static struct clk aux_clk = {
.name = "aux_clk",
.parent = &ref_clk,
+ .flags = CLK_PLL,
.fixed_divisor = 1,
};
+static struct clk clkout1_clk = {
+ .name = "clkout1",
+ .parent = &aux_clk,
+ .flags = CLK_PLL,
+ /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
+};
+
+static struct clk clkout2_clk = { /* PLL1.SYSCLKBP */
+ .name = "clkout2",
+ .parent = &ref_clk,
+ .flags = CLK_PLL,
+ .fixed_divisor = 3,
+ /* NOTE: clkout2 can be externally gated by muxing GPIO-17 */
+};
+
+static struct clk clkout3_clk = {
+ .name = "clkout3",
+ .parent = &pll2_clk,
+ .flags = CLK_PLL,
+ .fixed_divisor = 8,
+ /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
+};
+
static struct clk sysclk1_clk = {
.name = "SYSCLK1",
.parent = &pll1_clk,
+ .flags = CLK_PLL,
.fixed_divisor = 2,
};
static struct clk sysclk2_clk = {
.name = "SYSCLK2",
.parent = &pll1_clk,
+ .flags = CLK_PLL,
.fixed_divisor = 4,
};
-static struct clk sysclk5_clk = {
- .name = "SYSCLK5",
+static struct clk vpbe_clk = { /* pll1.sysclk3 */
+ .name = "vpbe",
.parent = &pll1_clk,
- .fixed_divisor = 6,
+ .flags = CLK_PLL,
+ /* NOTE: PLLDIV3 is programmable! result should be 27 MHz */
+};
+
+static struct clk vpss_clk = { /* pll1.sysclk4 */
+ .name = "vpss",
+ .parent = &pll1_clk,
+ .flags = CLK_PLL,
+ .fixed_divisor = 4,
+ /* NOTE: PLLDIV4 is programmable! 2 or 4 */
};
static struct clk arm_clk = {
.name = "ARMCLK",
.parent = &sysclk1_clk,
- .lpsc = -1,
- .flags = ALWAYS_ENABLED,
+ .flags = ALWAYS_ENABLED | CLK_PLL,
+};
+
+/*
+ * NOT LISTED below, but turned on by PSC init:
+ * - in SyncReset state by default
+ * .lpsc = DAVINCI_LPSC_VPSSMSTR, .parent = &vpss_clk,
+ * .lpsc = DAVINCI_LPSC_VPSSSLV, .parent = &vpss_clk,
+ * .lpsc = DAVINCI_LPSC_TPCC,
+ * .lpsc = DAVINCI_LPSC_TPTC0,
+ * .lpsc = DAVINCI_LPSC_TPTC1,
+ *
+ * NOT LISTED below, and not touched by Linux
+ * - in SyncReset state by default
+ * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
+ * .lpsc = DM355_LPSC_RT0, .parent = &aux_clk,
+ * .lpsc = DAVINCI_LPSC_MEMSTICK,
+ * .lpsc = 41, .parent = &vpss_clk, // VPSS DAC
+ * - in Enabled state by default
+ * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
+ * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
+ * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
+ * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
+ * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
+ * .lpsc = DAVINCI_LPSC_CFG27, // "test"
+ * .lpsc = DAVINCI_LPSC_CFG3, // "test"
+ * .lpsc = DAVINCI_LPSC_CFG5, // "test"
+ */
+
+static struct clk mjcp_clk = {
+ .name = "mjcp",
+ .parent = &sysclk1_clk,
+ .lpsc = DAVINCI_LPSC_IMCOP,
};
static struct clk uart0_clk = {
@@ -108,97 +179,126 @@ static struct clk i2c_clk = {
static struct clk asp0_clk = {
.name = "asp0_clk",
- .parent = &sysclk5_clk,
+ .parent = &sysclk2_clk,
.lpsc = DAVINCI_LPSC_McBSP,
};
static struct clk asp1_clk = {
.name = "asp1_clk",
- .parent = &sysclk5_clk,
+ .parent = &sysclk2_clk,
.lpsc = DM355_LPSC_McBSP1,
};
static struct clk mmcsd0_clk = {
.name = "MMCSDCLK0",
- .parent = &sysclk5_clk,
+ .parent = &sysclk2_clk,
.lpsc = DAVINCI_LPSC_MMC_SD,
};
static struct clk mmcsd1_clk = {
.name = "MMCSDCLK1",
- .parent = &sysclk5_clk,
+ .parent = &sysclk2_clk,
.lpsc = DM355_LPSC_MMC_SD1,
};
static struct clk spi0_clk = {
.name = "SPICLK",
- .parent = &sysclk5_clk,
+ .parent = &sysclk2_clk,
.lpsc = DAVINCI_LPSC_SPI,
};
static struct clk spi1_clk = {
.name = "SPICLK1",
- .parent = &sysclk5_clk,
+ .parent = &sysclk2_clk,
.lpsc = DM355_LPSC_SPI1,
};
static struct clk spi2_clk = {
.name = "SPICLK2",
- .parent = &sysclk5_clk,
+ .parent = &sysclk2_clk,
.lpsc = DM355_LPSC_SPI2,
};
static struct clk gpio_clk = {
.name = "gpio",
- .parent = &sysclk5_clk,
+ .parent = &sysclk2_clk,
.lpsc = DAVINCI_LPSC_GPIO,
};
static struct clk aemif_clk = {
.name = "AEMIFCLK",
- .parent = &sysclk5_clk,
+ .parent = &sysclk2_clk,
.lpsc = DAVINCI_LPSC_AEMIF,
.usecount = 1,
};
static struct clk pwm0_clk = {
.name = "PWM0_CLK",
- .parent = &ref_clk,
+ .parent = &aux_clk,
.lpsc = DAVINCI_LPSC_PWM0,
};
static struct clk pwm1_clk = {
.name = "PWM1_CLK",
- .parent = &ref_clk,
+ .parent = &aux_clk,
.lpsc = DAVINCI_LPSC_PWM1,
};
static struct clk pwm2_clk = {
.name = "PWM2_CLK",
- .parent = &ref_clk,
+ .parent = &aux_clk,
.lpsc = DAVINCI_LPSC_PWM2,
};
static struct clk pwm3_clk = {
.name = "PWM3_CLK",
- .parent = &ref_clk,
+ .parent = &aux_clk,
.lpsc = DM355_LPSC_PWM3,
};
+static struct clk timer0_clk = {
+ .name = "timer0",
+ .parent = &aux_clk,
+ .lpsc = DAVINCI_LPSC_TIMER0,
+};
+
+static struct clk timer1_clk = {
+ .name = "timer1",
+ .parent = &aux_clk,
+ .lpsc = DAVINCI_LPSC_TIMER1,
+};
+
+static struct clk timer2_clk = {
+ .name = "timer2",
+ .parent = &aux_clk,
+ .lpsc = DAVINCI_LPSC_TIMER2,
+};
+
+static struct clk timer3_clk = {
+ .name = "timer3",
+ .parent = &aux_clk,
+ .lpsc = DM355_LPSC_TIMER3,
+};
+
static struct clk usb_clk = {
.name = "USBCLK",
- .parent = &sysclk5_clk,
+ .parent = &sysclk2_clk,
.lpsc = DAVINCI_LPSC_USB,
};
static struct clk *dm355_clks[] __initdata = {
&ref_clk,
&pll1_clk,
- &pll2_clk,
&aux_clk,
+ &clkout1_clk,
+ &clkout2_clk,
+ &pll2_clk,
+ &clkout3_clk,
&sysclk1_clk,
&sysclk2_clk,
- &sysclk5_clk,
+ &vpbe_clk,
+ &vpss_clk,
&arm_clk,
+ &mjcp_clk,
&uart0_clk,
&uart1_clk,
&uart2_clk,
@@ -216,6 +316,10 @@ static struct clk *dm355_clks[] __initda
&pwm1_clk,
&pwm2_clk,
&pwm3_clk,
+ &timer0_clk,
+ &timer1_clk,
+ &timer2_clk,
+ &timer3_clk,
&usb_clk,
NULL,
};
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -17,6 +17,7 @@
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/clk.h>
+#include <linux/err.h>
#include <mach/hardware.h>
#include <asm/system.h>
@@ -313,10 +314,9 @@ static void __init davinci_timer_init(vo
/* init timer hw */
timer_init();
- if (cpu_is_davinci_dm646x())
- timer_clk = clk_get(NULL, "SYSCLK3");
- else
- timer_clk = clk_get(NULL, "ref_clk");
+ timer_clk = clk_get(NULL, "timer0");
+ BUG_ON(IS_ERR(timer_clk));
+ clk_enable(timer_clk);
davinci_clock_tick_rate = clk_get_rate(timer_clk);
clk_put(timer_clk);
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -401,7 +401,7 @@ static int davinci_i2s_probe(struct plat
struct resource *mem, *ioarea;
struct evm_snd_platform_data *pdata;
int ret;
- static const char *clocks[] = { "McBSPCLK", "McBSPCLK1", };
+ static const char *clocks[] = { "asp0_clk", "asp1_clk", };
if (pdev->id < 0 || pdev->id > ARRAY_SIZE(clocks))
return -EINVAL;
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