Gentlemen: Increasing the voltage incrementally is the correct way to test for ESD susceptibility.
There are indeed physical changes in the discharge risetime for different charge voltages. But there are other ways of explaining these window effects. I first encountered this issue in the mid 1980's, while ESD testing equipment that used singlechip microcontrollers. These were very slow devices with clock speeds of 1 to 4 MHz. They showed signgifcant ESD window effects. But because of their intrinsically slow speeds, I doubt that they were responding to subnanosecond ristime changes. Instead, I like the comparator/logic gate model to explain these window events. COMPARATOR/LOGIC GATE MODEL Suppose we have a logic gate with the following truth table: Inputs A&B HIGH > output LOW > (EUT functions normally) Inputs A&B LOW > output LOW > (EUT functions normally) Inputs A HIGH & B LOW > output HIGH > (EUT resets/fails) Inputs A LOW & B HIGH> output HIGH > (EUT resets/fails) Now suppose further that noise induced by ESD does not couple equally to both A & B. Lets say that the induced voltage at A is 70 percent of the induced voltage at B. Start with A & B inputs LOW with no noise present. At low ESD levels, both A&B inputs remain LOW, and the system functions normally. As we increase the ESD voltage, at some point the induced noise voltage will be high enough so that B is HIGH, while A is still LOW. >From the truth table above, the unit will now reset/fail. But as we increase the ESD level higher, now the noise voltage will drive both A & B HIGH, and the unit is now passing again. Just another model to put in your arsenal when you try to explain ESD window effects to a skeptical customer. Some customers will convert your testing rate into dollars per minute, and will be skeptical about things that increase the testing time. With those guys, you'll need every reasonable model you can lay your hands on. PS - Bear in mind, most modern digital IC's have thousands of gates built into their dies, and it only takes one gate to cause this type of window effect. Best regards Paul Cook NARTE Certified EMC Engineer Alpha EMC Inc 8540 West River Rd Minneapolis, Minnestoa 55444 Tel # (612)-561-2844 Fax #(612)-561-3400 E-mail [email protected] Specialty - EMC Consulting -----Original Message----- From: Scott Douglas <[email protected]> To: '[email protected]' <[email protected]> Cc: [email protected] <[email protected]>; [email protected] <[email protected]> List-Post: [email protected] Date: Friday, August 20, 1999 1:27 PM Subject: RE: EN50082-1:1997 & EN55024 > >Hi Benoit, > >I think that testing at voltage increments up to the standard limit (or >beyond) is necessary. We too had several products that failed at 2 or 3 kV >but never blinked at 8 kV. Testing to 8 kV only does meet the requirement >of the standard, but if my customers keep asking for their money back, what >good is the standard test? As for your hypothesis, I concur. Either one is >possible. I never did go after figuring out why, just how to fix it. The >solution would probably give a clue as to why, but it was long enough ago >that I forget what it was. > >Scott >[email protected] > >-----Original Message----- >From: [email protected] [SMTP:[email protected]] >Sent: Thursday, August 19, 1999 1:07 PM >To: [email protected]; [email protected] >Subject: Re: EN50082-1:1997 & EN55024 > > >Bonjour de Montreal, > >In another life, I was working for a EMC Test lab and we always used the >step by step procedure which was in the ESD Standard. We tested using this >procedure for years and we did encounter some products who failed at low >level ESD but had no problem at higher levels. > >We wondered what to conclude and had some hypothesis. > >1) may be the current path was different at higher level or >2) Lower levels might have a slightly longer rise time which tends to >produce >more energy in the lower part of the frequency spectrum where the EUT was >more sensible. > >Since the products were not staying in our hands for long we never had a >chance to investigate further. > >Comments ? >At 10:07 19-08-99 -0400, Jim Hulbert wrote: >>> .............Snip lots of other stuff. --------- This message is coming from the emc-pstc discussion list. To cancel your subscription, send mail to [email protected] with the single line: "unsubscribe emc-pstc" (without the quotes). For help, send mail to [email protected], [email protected], [email protected], or [email protected] (the list administrators).
