I concur, particularly with item 2. It is my understanding that the
frequency spectra is different at the lower levels. Meaning your are
stressing different frequencies. Not sure I fully understand why, if the
discharge waveform is described shouldn't it be the same rise time for all
voltage levels? That implies that the frequency content would be the same
throughout. 
Haven't given it a great deal of thought (I know what your thinking but
please spare me), but I certainly agree that I have seen lower levels cause
problems not seen at the higher discharge levels, and as a practice have
always stepped up in about 2k increments, and have gone significantly higher
than the IEC levels required when the test dealt with things people had to
touch to make it work - EG keyboards.
For what its worth.
Gary

        -----Original Message-----
        From:   Benoit Nadeau [SMTP:[email protected]]
        Sent:   Thursday, August 19, 1999 10:07 AM
        To:     Jim Hulbert; [email protected]
        Subject:        Re: EN50082-1:1997 & EN55024


        Bonjour de Montreal,

        In another life, I was working for a EMC Test lab and we always used
the
        step by step procedure which was in the ESD Standard. We tested
using this
        procedure for years and we did encounter some products who failed at
low
        level ESD but had no problem at higher levels.

        We wondered what to conclude and had some hypothesis.

        1) may be the current path was different at higher level or
        2) Lower levels might have a slightly longer rise time which tends
to produce 
        more energy in the lower part of the frequency spectrum where the
EUT was
        more sensible.

        Since the products were not staying in our hands for long we never
had a
        chance to investigate further.

        Comments ?
        At 10:07 19-08-99 -0400, Jim Hulbert wrote:
        >
        >
        >
        >Immunity test standards EN50082-1:1997 and EN 55024 call out the
basic
        standards
        >EN61000-4-2 and EN61000-4-5  for ESD and Surge.
        >
        >EN61000-4-2, Section 5 starts out "The preferential range of test
levels
        for the
        >ESD test is given in table 1.  Testing shall also be satisfied at
the lower
        >levels given in table 1."   EN61000-4-5, Section 5 contains similar
wording.
        >This is how we perform our compliance tests.   We start at the
lowest test
        >voltage levels from the respective tables and step up to the test
levels
        called
        >out in EN50082-1/ EN55024 (or higher, depending on our own in-house
product
        >spec.)
        >
        >However, I have noticed that some test labs go straight to the
levels
        called out
        >in EN 50082-1/EN55024 and skip testing at the lower levels.  I
believe this
        >approach is incorrect because it does not conform to the
requirements of the
        >basic standard and is simply not a complete test.   As explained in
        EN61000-4-5,
        >the non-linear current-voltage characteristics of the equipment
under test
        >should be considered and the test voltage should therefore be
increased by
        steps
        >up to the test level specified in the product standard or test
plan.   The
        same
        >rationale applies to ESD testing where current-voltage
characteristics are
        also
        >non-linear.
        >
        >How do others approach these tests?  Are we adding unnecessary test
time by
        >starting at lower test voltages and stepping our way up or are the
test labs
        >that go straight to the maximum test levels overlooking an
important
        aspect of
        >the testing?
        >
        >Jim Hulbert
        >Senior Engineer-EMC
        >Pitney Bowes



        
--------------------------------------------------------------------------
        Benoit Nadeau, ing. M.ing. (P.Eng., M.Eng)
        Gerant du Groupe Conformite (Conformity Group Manager)
        Matrox <http://www.matrox.com/>
        
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