Let's say, part of a pcb stack looks like this --- GND1 - SIGNAL - GND2
GND1 is solid copper fill SIGNAL layer consists of high frequency lines LVDS, USB3.0, etc. GND2 should be solid copper fill, but some traces are in that layer due to space utilization reason. These traces are crossing 90 degrees the traces in SIGNAL layer. These traces in the GND2 will create gaps and therefore problems for the return current for the high frequency lines I SINAL layer. But does it matter, as long as the GND1 layer is 100% filled, and there is no disruption of the return current path for the traces in the adjacent SIGNAL layer? Best regards Amund Westin - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. To post a message to the list, send your e-mail to <[email protected]> All emc-pstc postings are archived and searchable on the web at: http://www.ieee-pses.org/emc-pstc.html Attachments are not permitted but the IEEE PSES Online Communities site at http://product-compliance.oc.ieee.org/ can be used for graphics (in well-used formats), large files, etc. Website: http://www.ieee-pses.org/ Instructions: http://www.ieee-pses.org/list.html (including how to unsubscribe) List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas <[email protected]> Mike Cantwell <[email protected]> For policy questions, send mail to: Jim Bacher: <[email protected]> David Heald: <[email protected]>
