Looking in REGMAP4 of the m5i20, CCR bit 5 ClearOnIndex sounds like it fits the description of emc2's index-enable. Do any of the m5i20's pins connect to the m5i20 CCR bit 5?
CCR (Counter Control Register) Bit definitions: BIT9 CounterMode 0 = quadrature 1 = up/down BIT8 InputFilter 0 = No filter 1 = ~2 MHz input filter BIT7 Inbit BIT6 LCountenable 0 = count disabled 1 = counting enabled BIT5 ClearOnIndex 0 = no COI 1 = clear counter on index BIT4 Latchedindex 0 = no index 1 = index detected BIT3 IndexPolarity 0 = index active low 1 = index active high BIT2 Index Real time index status (reads) counter clear (writes) BIT1 B Real time input A status (read only) BIT0 A Read time input B status (read only) Thanks, RogerN ------------------------------------------------------------------------- This SF.net email is sponsored by DB2 Express Download DB2 Express C - the FREE version of DB2 express and take control of your XML. No limits. Just data. Click to get it now. http://sourceforge.net/powerbar/db2/ _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
