Peter C. Wallace wrote: > The 5I20 is no different, At power up or PC reset, the I/O pins are in > a defined state (all high) and will not change until the FPGA is programmed > and EMC enables the outputs. OK, I guess the difference is the SSR locations are actually ON my board, so there is no choice on how to hook them up, or which polarity is "on". If you bring the logic signal out to a terminal, then the used can decide whether +5 is on or ground is on. This all high state disables all 7I33/7I65 analog > outputs and Opto22 or 7I37 output switches. In addition the HostMot Firmware > has a watchdog that can disable analog outputs (Its sets Enables false and > PWMs off at timeout). The current (HostMot) watchdog does not affect the GPIO > pins but new HostMot2s watchdog also controls the GPIO pins so a timeout will > restore all IO to the startup state (and set a flag indicating that the > watchdog has bitten) > > > I think Erics problem has to do with the desired GPIO bit state at > startup (looks like he wants low at startup), which will require either an > inverter or a changing the pullup resistors to pulldown resistors to change > the startup GPIO state from high to low. The user really MUST follow what the board is pre-programmed to provide as a safety "off" state. Having a lsthe spindle start up without user command is pretty bad, but having a LASER turn on without command could be a real disaster, as there'd be no warning or acceleration time! This kind of careless CNC retrofit is totally unacceptable, and one of those things that keeps me up at night! (If you haven't made this clear in your manuals, you might want to see if it can be stated more boldly. Not a criticism, just that some people are really careless in this regard.)
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