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Also see ATA/ATAPI-7 clause "J.1.8 ATAPI PACKET PIO data out"... In this description you will find that it is the SATA host contoller's job to switch from BSY=0 DRQ=1 to BSY=1 status once the last word of data in the DRQ block has been transferred to the host controller's transmit FIFO. Is there a spec for how much time the host controller has to make this status switch? Probably not. But if the host controller is correctly emulating a PATA host controller then that switch will happen when the last data word is transferred into the controller (from the host). That should happen well within the 100ns delay time that is required on the host side (definitely within the old 400ns delay time).
I'm starting to think you have a host controller problem perhaps caused by something your host software is doing that confuses the host controller. There is no way you should be seeing BSY=0 DRQ=1 immediately after the transfer of the last word in a DRQ data block, and if you are seeing this then that would tell me the host controller has a bug or the host side s/w is very slow (and the device is now ready to transfer the next DRQ block).
Hale -- ++ Hale Landis ++ www.ata-atapi.com ++
