A DRC question/problem...
I've built a thermal dissipation area. Top & bottom layers are polygon pours; I have
two internal planes, which were already split, so I had to add a third split to each
for the thermal pads. I tried to follow the help file directions, wrapping the
boundary of one split around the other. The four layers are 'stapled' with a series
of vias. The device is SM, and its pad is in the center of the top-layer polygon.
The net only contains that single pin. The polygons, planes, and vias are all
assigned the same net.
Now when I run DRC, I get:
Processing Rule: Broken-Net constraint (on the board)
Violation: Net FET-pad-A
Warning - Connection to overlapping split planes.
I don't understand what it's complaining about. How can I have a broken net when it's
a single-pin net? Any suggestions on how to fix this?
TIA,
Dwight
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