At 11:35 AM 5/21/01 -0700, Dwight Harm wrote:
>"The CPC5602C is a ...[FET with] a typical on-resistance of 8 ohms, a
>breakdown voltage exceeding 350V and is designed in a SOT-223 package. In
>some current limiting conditions, the FET is required to dissipate almost 2
>watts of power. The FET must have a sufficient heat sink to handle this
>thermal load. If the heat sink is integrated into the PCB layout, a heat
>sink may be designed with: 4 PCB layers, a heat sink area of 1.5 cm x 0.4 cm
>and all 4 layers connected by 20 plated through holes. This provides a total
>area of 5.4 sq. cm. This is sufficient for the expected heat dissipation of
>the FET during operation under current limit."
>
>I couldn't quite come up with 5.4 sq. cm from their measurements,
Gee, I wonder why.... The total surface is 1.2 sq. cm. Whoever wrote that,
it appears, did not have the foggiest idea what he was doing, or he had not
had his morning coffee yet. Letting this settle for a day more, I'm 100%
certain that *isolated* inner planes will not improve heat sinking over no
inner planes. Intact inner planes may very well help; indeed, they may be
the most effective part of the heat sink design. FR4 is not as good a heat
conductor as copper, for sure, but there is only a thin layer of FR4
between the part and an inner plane.
We might assume that the manufacturer has thoroughly tested the thermal
issues, but such assumptions are not always true. It's hard to find good
help....
> unless you
>count BOTH sides of EACH layer, and count the hole plating as two-sided
>also! Anyway, my pads are about 0.8 sq cm (per layer), and their spec is
>0.6 sq cm, so I feel pretty safe.
Don't. That discussion said two watts, and the part spec said 2.5. That's a
significant amount of heat. I don't have the formulas or any charts handy,
but fried PCBs are expensive, especially if they happen to the customer in
the field. Absolutely, whatever you do, test the PCB under full and
continuous fault conditions to make sure it's okay before releasing it, and
I strongly recommend doing a thermal transfer calculation. If you don't
know how to do that, I'm pretty sure that someone here will be able to
help. You will never regret having too much heat sink; once you have a
proto, you will be able to determine experimentally how effective your sink
is and, if you need the space in later revisions, you may be able to cut it
down.
If the plated holes are not under a part, they probably won't hurt and they
might help a little. As I mentioned, the effectiveness of holes remains a
bit controversial, unless there is forced air.
Someone should have the information relatively handy regarding what board
surface area is adequate for a given heat rise at a certain power level. CP
Clare should be able to provide the thermal resistance of the part itself.
But I didn't see it in the spec.
Just for grins, I looked in one of the tattered data books lying around
(yes, kids, back in the old days there used be a thing called "books"); a
TO-220 LM78XX series regulator from National had these specs: Maximum
junction temperature, T package, 125 degrees C. Thermal resistance, 4
degrees C per watt junction to case and 50 degrees C. per watt case to ambient.
So with no heat sink and say 50 degrees ambient, 2.5 watts dissipation, the
junction will be 10 degrees above the case, and the case will be 125
degrees above ambient. That would come to 185 degrees at the junction, well
beyond spec. A TO-220 case has a surface area of about 4 sq. cm. To keep
the case to ambient rise to 65 degrees, the surface area needs to be
roughly 8 sq cm. I'd expect this part to need roughly the same to be safe.
*But the inner planes may add quite a bit of effective area.*
30 dase ago i cudent even spel injineer and now I are one. Do the
calculation and do it right.
[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433
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