At 01:03 PM 5/18/01 -0700, Dwight Harm wrote:
>John (et al),
>All the vias seems well inside the boundaries. I did find that if I delete
>all the vias, the warning goes away. Putting just one via back gets the
>warning.
>
>As another experiment, I tried changing the net assigned to the split plane
>(on my ground plane) to No Net, and to some random net. In both cases the
>warning did not change, nor were additional warnings issued, which seems
>odd, since the vias would be causing a short between two nets.
>
>I'm not even sure what Protel means by "overlapping". The top & bottom
>polygons, and the inner plane splits, all have identical (I think!)
>boundaries.
Mr. Harm uploaded a cut-down version of the file which shows his problem to
the filespace for protel-users-issues. This enabled me to quickly determine
what is going on. Yes, Mr. Harm was probably right when he said that he did
not know what "overlapping" meant in this context. Or he did not recognise
that he had overlapping splits.
Looking at the power plane, what we see appears to be two split plane areas
connected by a single blowout trace. However, that is not a trace, it is an
extension which is the outline of a single split plane which includes both
the areas.
He has a via in the right-hand area, and this via generates the DRC message:
Processing Rule : Broken-Net Constraint ( (On the board ) )
Violation Net FET-PAD-A
Warning - Connection to overlapping split planes
Rule Violations :1
Since that Net is the net he has assigned to that plane section, it is easy
to see why he does not understand the error. The error message does not say
what the other split plane is.
However, double-clicking on the right-hand area pops up the selection window:
Split Plane (VCC33) on Power
Split Plane Net (FET-PAD-A) on Power
There is another split plane on the same layer and in the same space. To
see it, try to pick up the right hand split plane. Select the plane
(VCC33); when you move it around, it is this rectangular dumbell shape. If
you delete the plane FET-PAD-A entirely, the only change you will see on
the layer is that the outline of the right hand section becomes thinner.
If that via is allowed to connect to the power plane, it will short the
nets, as far as Protel is concerned, VCC33 and FET-PAD-A. Protel doesn't
know that FET-PAD-A is a dummy net for thermal purposes.
Now, I have never before seen such a net; but if a pin of a device will
short to the plane or copper pour, and that pin is an NC pin, then this
would be the way to get the pin to connect instead of being isolated.
No-net planes do not connect to no-net pads.
Now, the mystery is solved, as far as I can see. In the process, I did
uncover a solid bug, as far as I can tell, the file is also in the
protel-users-issues filespace (I gave the URL in my previous post in this
thread). Maybe someone will tell me something I have overlooked; we all
have blind spots.
Some more comments: The dumbell-shaped split plane strikes me as unlikely
to be useful unless one actually wants to break up the power plane that
way. I would guess that when it was placed, Mr. Harm thought that to have
two split plane areas assigned to the same net, he needed to have one split
plane polygon extended in this way. That is not true. You can make as many
separated split plane areas as you like with the same net; they do not have
to be connected on the plane layer and they will create no error message
unless there is some pad of the same net in their areas which is not
connected to the rest of the net. If one of these planes is not physically
connected to any net, no error message is generated. It's the same with
floating net-assigned copper or vias on any layer. They do not generate an
error unless pads which are assigned to the net are unconnected.
(Free pads *do* generate an error, which is another difference between free
pads and vias.)
Now, as to Mr. Harm's original intention, I'm not going to claim to be a
thermal engineer, so caveat emptor. Isolated thermal copper on inner layers
is of questionable utility for heat-sinking. If one is communicating heat
to the edge of the board, it might be useful, otherwise it will not change
the thermal resistance of the assembly except maybe to *increase* it a tiny
bit. For an electrical analogy, consider strip resistors of, say, 10 ohms
per mil of length. Let's represent Mr Harm's board with a single resistor,
62 mils long. Its resistance will be 620 ohms. Now, let's split it into two
31 mil lengths, putting 1.4 mils of other material in the middle. The new
thermal resistance will be 620 ohms plus the 1.4 times the resistance of
the other material, which will be greater than zero. Unless that material
is superconducting, the resistance of the assembly will increase.
Inner layers typically *add* thickness to the board. Of course, one can
reduce the other layer thicknesses, but it is that reduction which will
improve thermal conductivity to the other side of the board, not the
copper. If you hold the board thickness constant and convert some of the
board material to copper, yes, that will lower thermal resistance, but
unless that copper is very thick, which you are not going to make with
standard fabrication process, the effect will be negligible, not worth the
effort. Isn't Invar used for this? (I've never had occasion to design with it.)
It has been alleged that putting many plated holes through the board will
improve the capacity of a heat sink. There is some conflicting opinion on
this and only a little actual testing has been published. Having heat
sinking area on both sides of the board will help; and vias from the top of
the board to the bottom may also help a little. The holes probably don't
help much because the loss of conductive material due to the holes takes
away the improvement from convective flow through the holes and increased
transfer surface inside the holes. Plugged vias might be best. As I said,
it is controversial, but if there is forced air conduction through the
holes, I have seen evidence that holes can make a very substantial
improvement. Otherwise it is probably not worth the effort.
The most significant source of heat resistance is thermal transfer between
the heat sink and ambient air or free space. Increasing the effective sink
surface area is about the only way to improve this; inner layers do not do
this unless they conduct to some other external surface.
Another aspect of the stack-up in Mr. Harm's board is that there was only
one inner plane. But probably he eliminated the other planes in cutting the
board down for posting.
Anyway, I thank Mr. Harm for posting his board; it gives us an opportunity
not only to solve the immediate problem but also to bring up many issues,
some of which discussion might be useful to someone someday, if not today.
[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/subscrib.html
* - or email -
* mailto:[EMAIL PROTECTED]?body=leave%20proteledaforum
*
* Contact the list manager:
* mailto:[EMAIL PROTECTED]
*
* Browse or Search previous postings:
* http://www.mail-archive.com/[email protected]
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
