If you have a via that has any portion of its "region" (i.e. via
diameter plus clearance) that touches the split, Protel can come
to the conclusion that the via is connected to planes on both
sides of the split.
Could this be the case?
John Haddy
> -----Original Message-----
> From: Steve Smith [mailto:[EMAIL PROTECTED]]
> Sent: Saturday, 19 May 2001 12:20 AM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] DRC - overlapping spliit planes message
>
>
> I've noticed before that Protel doesn't like overlapping split planes
> and gives all kinds of un-routed net warnings stating the error you
> see. I've yet to find a design rule setting that will get rid of this.
> Anyone else have any better luck?
>
> Steve Smith
> Product Engineer
> Staco Energy Products Co.
> Web Site: www.stacoenergy.com
>
>
>
> > -----Original Message-----
> > From: Dwight Harm [mailto:[EMAIL PROTECTED]]
> > Sent: Friday, May 18, 2001 4:53 AM
> > To: Protel EDA Forum
> > Subject: [PEDA] DRC - overlapping spliit planes message
> >
> >
> > A DRC question/problem...
> > I've built a thermal dissipation area. Top & bottom layers
> > are polygon pours; I have two internal planes, which were
> > already split, so I had to add a third split to each for the
> > thermal pads. I tried to follow the help file directions,
> > wrapping the boundary of one split around the other. The
> > four layers are 'stapled' with a series of vias. The device
> > is SM, and its pad is in the center of the top-layer polygon.
> > The net only contains that single pin. The polygons,
> > planes, and vias are all assigned the same net.
> >
> > Now when I run DRC, I get:
> >
> > Processing Rule: Broken-Net constraint (on the board)
> > Violation: Net FET-pad-A
> > Warning - Connection to overlapping split planes.
> >
> > I don't understand what it's complaining about. How can I
> > have a broken net when it's a single-pin net? Any
> > suggestions on how to fix this?
> >
> > TIA,
> > Dwight
> >
>
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