At 02:55 AM 5/20/01 -0700, Dwight Harm wrote:
>My thanks to Mr. Lomax for finding & analyzing my uploaded file, long
>before I posted about it!
As the owner/moderator of that group, I am notified of all file uploads.
Other moderators can be added, which is the plan. That filespace, however,
is not for discussion, but for examples of bugs described in the bug
database (which presently lives with [EMAIL PROTECTED]). Since
there is no bug involved here (other than one which is represented in
another file); I expect to remove Mr. Harm's files from that filespace at
some time in the future. The discussion on this list is adequate for
educational purposes.
>- I'm doing the "heat sink" in this fashion -- with vias, and including
>electrically-isolated copper on inner layers -- because that is the
>manufacturer's recommendation (CP Clare). Note that the article
>referenced by Mr. Cary appears to deal with 2-layer boards, so the results
>may or may not be applicable.
The experimental results were for two-layer boards, true, but the logic of
the explanation of the results, which I detailed in my post (and went
farther than the original article in showing the math of it), still
applies. The presence of copper in an inner layer will not significantly
improve heat transfer through the board. It won't hurt (in this case,
because there is already a plane layer there), but there is no necessity to
have it connected electrically. It will be connected thermally through the
board material; my sense is that additional heat transfer through connected
vias will not be significant.
A manufacturer's engineer very likely had the bright idea of adding inner
plane copper; one can understand how an engineer might intuit that it would
be helpful. But there is a huge amount of untested theory floating around
in the printed circuit design business and precious little actual
experiment. So perhaps Clare made a demo board with the inner copper (or
they never even tested the inner copper idea, demoing with only external
sinks), and it worked, and they never made the board without the copper for
a comparison.
From my theoretical analysis, which I reported, I expect that the effect
on the operating temperature of the device, between a thermally-connected
inner copper area and one which was, say, simply the unsplit plane area,
would be unmeasurable. There are others on this list who, I also would
expect, would have both more training and experience than I in this area.
If I was faced with the design myself, I would probably ask on the
Designer's Council list, and I would read the answers carefully. Some of
them might well be wrong. I'd want to understand which way to go *and why*.
But I will say that I'm pretty certain.
That an unidentified manufacturer's engineer recommends something does not
necessarily mean that it's a good idea, especially if the engineer is not
in his area of specialization. CP Clare is a relay company and I don't
think they design very many PC boards.
This got my curiosity up, so I tracked down the part which Mr. Harm is
using. There is only one SOT-223 part made by CP Clare, if I am correct,
the CPC5602 DAA. I read the app notes, which did not mention heat sinking
of the part as far as I could find. There is a reference design, available
as gerber. I downloaded the files and loaded them. CAMtastic is really
cool: not only is it practically one-button to load the files; the files
were generated with differing offsets and CAMtastic aligned them
automatically on command, all I had to do was click on the outline.
The files had been generated with Power PCB (Boo ... hiss ....). It is a
two-sided board. There are heat sink areas on the top and bottom, and they
are tacked with vias. The vias are thermally relieved. There is plenty of
room for the heat sinks to be larger on both sides of the board, they could
be doubled in area. The heat sinks have solder mask over them. To be
explicit, there are no inner planes on this design.
My conclusion about this design is that it was not correctly done to
optimize thermal properties. There is no reason to thermally relieve the
vias, the solder mask will raise thermal resistance slightly (for the same
reasons as I have described with inner plane copper, though, this is
probably not a large effect), and the thermal resistance could be halved by
increasing the heat sink copper areas on both sides of the board. The part
can dissipate 2.5 watts. I'd say that the area should be increased as much
as possible. Whether or not a metal heat sink should be attached in some
way, I'd want to calculate, and I don't have enough information to do it.
Normally I don't deal with these things to that level, I just optimize the
PCB part of things, being given a schematic and related instructions (like
put a heat sink on such and such a part).
Mr. Harm, you should increase the heat sink areas if you can. Use copper
pour on the top and bottom to do this, and set the vias for direct connect.
This, by lowering thermal resistance between the heat sink areas and the
ambient air, will do much more to improve thermal performance than would
any possible effect from inner plane copper. Allow the unbroken normal
inner planes to be under the part because they may indeed help with heat
dissipation; they will carry heat out from under the part to the rest of
the board. Use 1 ounce copper on the inner planes if possible. It is the
split plane that will not help, because it does not increase thermal
transfer area.
>- Finally, Mr. Lomax is exactly correct in diagnosing my problem with the
>split planes. What I was attempting to do was follow the diagram shown in
>the help file under the topic "Using multiple split planes in a PCB
>design". The idea is that you cannot merely draw another split plane in
>the middle of the first split plane -- you must extend/deform the boundary
>between the default plane and the split plane to create a "hole", and
>within this hole you draw the boundary of the third split.
As another user noted, the problem with this technique is that it can break
up the ground plane, something which one should prefer to avoid. This
particular part I would expect, however, to be near the board edge because
it is a DAA, which will be connected directly to a phone line. Splitting
off a plane at the board edge does not do as much damage to the plane
integrity.
For those who are not familiar with this, return currents on fast-rise
signals will flow in the plane immediately beneath the trace; if that plane
is broken, they are forced to detour, which increases loop area, which
raises inductance, which causes radiation and reflections. So where one
must split a ground plane, it is appropriate to avoid routing fast-rise
signals over such a split. If the split is in the middle of the board, this
makes for routing difficulties and increased trace lengths, but if it is at
the edge, it will be less of a problem.
I do not like that the characteristics of Protel split plane polygons force
copper to be distributed in certain ways. Only a little more intelligence
in the planes would make it allowable for splits to be nested, and there
would be no need for the kind of pattern Mr. Harm found in the help file.
You want to split a plane, no problem: using polygons, you divide the plane
into areas without restriction. If an copper remains which is ambiguously
assigned, and there is a hole tghrough that copper from a pad or via
assigned to one of the possible nets, then an error message will be
generated (and the pad or via will not be connected to the plane). Nested
split planes are not ambiguous if one of them is entirely contained in another.
However, as Protel PCB is not now so configured, if one needed to do what
Mr. Harm wanted to do with this board, it might be better to use a copper
pour, which explicitly places copper. Besides, copper pours DRC completely,
whereas split planes can miss errors caused by lack of copper from, for
example, a pad needing connection being surrounded with vias whose blowouts
intersect so that no connection path from the pad hole remains to the rest
of the plane. Protel does not detect this. (It's actually a moderately
difficult problem; it takes a lot of calculation to solve it, even though
the eye can find it quickly. The eye is an efficient flood router.) The
down side of copper pours is, of course, that they create a lot of
primitives, and thus increase file sizes and plot sizes.
[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433
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