Steve,
Initially I had the boundary tracks just touching (10mil tracks on 10mil
centers). Now I've increased them to 12 mils, so the boundaries overlap,
which is what the help file indicates ("Using multiple Split Planes in a PCB
design"), and still got the same result. I then pulled the top & bottom
polygon planes in a bit, so they're actually 5 mils smaller (inside of) the
split planes, and still get the error.
I also tried narrowing the split-plane boundaries down to 8mil, resulting in
a tiny gap between the boundary tracks, and that still gets the same error.
Dwight.
> -----Original Message-----
> From: Steve Smith [mailto:[EMAIL PROTECTED]]
> Sent: Friday, May 18, 2001 1:25 PM
>
> Dwight,
> Do the Split planes touch each other at all?
> This will cause the error statement.
>
> Steve Smith
> Product Engineer
> Staco Energy Products Co.
> Web Site: www.stacoenergy.com
>
> > -----Original Message-----
> > From: Dwight Harm [mailto:[EMAIL PROTECTED]]
> > Sent: Friday, May 18, 2001 4:03 PM
> >
> > John (et al),
> > All the vias seems well inside the boundaries. I did find
> > that if I delete
> > all the vias, the warning goes away. Putting just one via
> > back gets the
> > warning.
> >
> > As another experiment, I tried changing the net assigned to
> > the split plane
> > (on my ground plane) to No Net, and to some random net. In
> > both cases the
> > warning did not change, nor were additional warnings issued,
> > which seems
> > odd, since the vias would be causing a short between two nets.
> >
> > I'm not even sure what Protel means by "overlapping". The
> > top & bottom
> > polygons, and the inner plane splits, all have identical (I think!)
> > boundaries.
> >
> > Dwight.
>
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