This patch shares the builtins and md patterns from avx10.2 and
vnniint{8,16} for avx10v1aux.
gcc/ChangeLog:
* config/i386/i386-builtin.def (BDESC): Share builtin between avx10.2,
vnniint{8,16} and avx10v1aux.
* config/i386/i386-builtins.cc (def_builtin): Ditto.
* config/i386/i386-expand.cc (ix86_check_builtin_isa_match): Ditto.
* config/i386/i386.md: Add isa target avx10v1aux.
* config/i386/sse.md: Enable instructions for avx10v1aux.
Co-authored-by: Venkataramanan Kumar <[email protected]>
---
gcc/config/i386/i386-builtin.def | 308 +++++++++++++++----------------
gcc/config/i386/i386-builtins.cc | 5 +-
gcc/config/i386/i386-expand.cc | 9 +
gcc/config/i386/i386.md | 4 +-
gcc/config/i386/sse.md | 74 ++++----
5 files changed, 206 insertions(+), 194 deletions(-)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index e2b7714d4c3..8f94261a9b2 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -2773,32 +2773,32 @@ BDESC (OPTION_MASK_ISA_AVX512VNNI |
OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpdpws
BDESC (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL, 0,
CODE_FOR_vpdpwssds_v4si_maskz, "__builtin_ia32_vpdpwssds_v4si_maskz",
IX86_BUILTIN_VPDPWSSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
/* AVXVNNIINT8 */
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssd_v8si, "__builtin_ia32_vpdpbssd256",
IX86_BUILTIN_VPDPBSSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssds_v8si, "__builtin_ia32_vpdpbssds256",
IX86_BUILTIN_VPDPBSSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsud_v8si, "__builtin_ia32_vpdpbsud256",
IX86_BUILTIN_VPDPBSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsuds_v8si, "__builtin_ia32_vpdpbsuds256",
IX86_BUILTIN_VPDPBSUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuud_v8si, "__builtin_ia32_vpdpbuud256",
IX86_BUILTIN_VPDPBUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuuds_v8si, "__builtin_ia32_vpdpbuuds256",
IX86_BUILTIN_VPDPBUUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssd_v4si, "__builtin_ia32_vpdpbssd128",
IX86_BUILTIN_VPDPBSSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssds_v4si, "__builtin_ia32_vpdpbssds128",
IX86_BUILTIN_VPDPBSSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsud_v4si, "__builtin_ia32_vpdpbsud128",
IX86_BUILTIN_VPDPBSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsuds_v4si, "__builtin_ia32_vpdpbsuds128",
IX86_BUILTIN_VPDPBSUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuud_v4si, "__builtin_ia32_vpdpbuud128",
IX86_BUILTIN_VPDPBUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuuds_v4si, "__builtin_ia32_vpdpbuuds128",
IX86_BUILTIN_VPDPBUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v8si, "__builtin_ia32_vpdpbssd256",
IX86_BUILTIN_VPDPBSSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v8si,
"__builtin_ia32_vpdpbssds256", IX86_BUILTIN_VPDPBSSDSV8SI, UNKNOWN, (int)
V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v8si, "__builtin_ia32_vpdpbsud256",
IX86_BUILTIN_VPDPBSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v8si,
"__builtin_ia32_vpdpbsuds256", IX86_BUILTIN_VPDPBSUDSV8SI, UNKNOWN, (int)
V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v8si, "__builtin_ia32_vpdpbuud256",
IX86_BUILTIN_VPDPBUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v8si,
"__builtin_ia32_vpdpbuuds256", IX86_BUILTIN_VPDPBUUDSV8SI, UNKNOWN, (int)
V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v4si, "__builtin_ia32_vpdpbssd128",
IX86_BUILTIN_VPDPBSSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v4si,
"__builtin_ia32_vpdpbssds128", IX86_BUILTIN_VPDPBSSDSV4SI, UNKNOWN, (int)
V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v4si, "__builtin_ia32_vpdpbsud128",
IX86_BUILTIN_VPDPBSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v4si,
"__builtin_ia32_vpdpbsuds128", IX86_BUILTIN_VPDPBSUDSV4SI, UNKNOWN, (int)
V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v4si, "__builtin_ia32_vpdpbuud128",
IX86_BUILTIN_VPDPBUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT8 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v4si,
"__builtin_ia32_vpdpbuuds128", IX86_BUILTIN_VPDPBUUDSV4SI, UNKNOWN, (int)
V4SI_FTYPE_V4SI_V4SI_V4SI)
/* AVXVNNIINT16 */
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusd_v8si, "__builtin_ia32_vpdpwusd256",
IX86_BUILTIN_VPDPWUSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusds_v8si, "__builtin_ia32_vpdpwusds256",
IX86_BUILTIN_VPDPWUSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsud_v8si, "__builtin_ia32_vpdpwsud256",
IX86_BUILTIN_VPDPWSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsuds_v8si, "__builtin_ia32_vpdpwsuds256",
IX86_BUILTIN_VPDPWSUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuud_v8si, "__builtin_ia32_vpdpwuud256",
IX86_BUILTIN_VPDPWUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuuds_v8si, "__builtin_ia32_vpdpwuuds256",
IX86_BUILTIN_VPDPWUUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusd_v4si, "__builtin_ia32_vpdpwusd128",
IX86_BUILTIN_VPDPWUSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusds_v4si, "__builtin_ia32_vpdpwusds128",
IX86_BUILTIN_VPDPWUSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsud_v4si, "__builtin_ia32_vpdpwsud128",
IX86_BUILTIN_VPDPWSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsuds_v4si, "__builtin_ia32_vpdpwsuds128",
IX86_BUILTIN_VPDPWSUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuud_v4si, "__builtin_ia32_vpdpwuud128",
IX86_BUILTIN_VPDPWUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuuds_v4si, "__builtin_ia32_vpdpwuuds128",
IX86_BUILTIN_VPDPWUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v8si, "__builtin_ia32_vpdpwusd256",
IX86_BUILTIN_VPDPWUSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v8si,
"__builtin_ia32_vpdpwusds256", IX86_BUILTIN_VPDPWUSDSV8SI, UNKNOWN, (int)
V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v8si, "__builtin_ia32_vpdpwsud256",
IX86_BUILTIN_VPDPWSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v8si,
"__builtin_ia32_vpdpwsuds256", IX86_BUILTIN_VPDPWSUDSV8SI, UNKNOWN, (int)
V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v8si, "__builtin_ia32_vpdpwuud256",
IX86_BUILTIN_VPDPWUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v8si,
"__builtin_ia32_vpdpwuuds256", IX86_BUILTIN_VPDPWUUDSV8SI, UNKNOWN, (int)
V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v4si, "__builtin_ia32_vpdpwusd128",
IX86_BUILTIN_VPDPWUSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v4si,
"__builtin_ia32_vpdpwusds128", IX86_BUILTIN_VPDPWUSDSV4SI, UNKNOWN, (int)
V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v4si, "__builtin_ia32_vpdpwsud128",
IX86_BUILTIN_VPDPWSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v4si,
"__builtin_ia32_vpdpwsuds128", IX86_BUILTIN_VPDPWSUDSV4SI, UNKNOWN, (int)
V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v4si, "__builtin_ia32_vpdpwuud128",
IX86_BUILTIN_VPDPWUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVXVNNIINT16 |
OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v4si,
"__builtin_ia32_vpdpwuuds128", IX86_BUILTIN_VPDPWUUDSV4SI, UNKNOWN, (int)
V4SI_FTYPE_V4SI_V4SI_V4SI)
/* VPCLMULQDQ */
BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX512VL, 0,
CODE_FOR_vpclmulqdq_v2di, "__builtin_ia32_vpclmulqdq_v2di",
IX86_BUILTIN_VPCLMULQDQ2, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT)
@@ -3054,90 +3054,90 @@ BDESC (OPTION_MASK_ISA_AVX512VL,
OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_
BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16,
CODE_FOR_avx512vl_fmulc_v16hf_mask, "__builtin_ia32_vfmulcph256_mask",
IX86_BUILTIN_VFMULCPH256_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI)
/* AVX10.2. */
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v16si,
"__builtin_ia32_vpdpbssd512", IX86_BUILTIN_VPDPBSSDV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v16si,
"__builtin_ia32_vpdpbssds512", IX86_BUILTIN_VPDPBSSDSV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v16si,
"__builtin_ia32_vpdpbsud512", IX86_BUILTIN_VPDPBSUDV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v16si,
"__builtin_ia32_vpdpbsuds512", IX86_BUILTIN_VPDPBSUDSV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v16si,
"__builtin_ia32_vpdpbuud512", IX86_BUILTIN_VPDPBUUDV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v16si,
"__builtin_ia32_vpdpbuuds512", IX86_BUILTIN_VPDPBUUDSV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v16si_mask,
"__builtin_ia32_vpdpbssd_v16si_mask", IX86_BUILTIN_VPDPBSSDV16SI_MASK, UNKNOWN,
(int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v16si_maskz,
"__builtin_ia32_vpdpbssd_v16si_maskz", IX86_BUILTIN_VPDPBSSDV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v16si_mask,
"__builtin_ia32_vpdpbssds_v16si_mask", IX86_BUILTIN_VPDPBSSDSV16SI_MASK,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v16si_maskz,
"__builtin_ia32_vpdpbssds_v16si_maskz", IX86_BUILTIN_VPDPBSSDSV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v16si_mask,
"__builtin_ia32_vpdpbsud_v16si_mask", IX86_BUILTIN_VPDPBSUDV16SI_MASK, UNKNOWN,
(int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v16si_maskz,
"__builtin_ia32_vpdpbsud_v16si_maskz", IX86_BUILTIN_VPDPBSUDV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v16si_mask,
"__builtin_ia32_vpdpbsuds_v16si_mask", IX86_BUILTIN_VPDPBSUDSV16SI_MASK,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v16si_maskz,
"__builtin_ia32_vpdpbsuds_v16si_maskz", IX86_BUILTIN_VPDPBSUDSV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v16si_mask,
"__builtin_ia32_vpdpbuud_v16si_mask", IX86_BUILTIN_VPDPBUUDV16SI_MASK, UNKNOWN,
(int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v16si_maskz,
"__builtin_ia32_vpdpbuud_v16si_maskz", IX86_BUILTIN_VPDPBUUDV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v16si_mask,
"__builtin_ia32_vpdpbuuds_v16si_mask", IX86_BUILTIN_VPDPBUUDSV16SI_MASK,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v16si_maskz,
"__builtin_ia32_vpdpbuuds_v16si_maskz", IX86_BUILTIN_VPDPBUUDSV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v8si_mask,
"__builtin_ia32_vpdpbssd_v8si_mask", IX86_BUILTIN_VPDPBSSDV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v8si_maskz,
"__builtin_ia32_vpdpbssd_v8si_maskz", IX86_BUILTIN_VPDPBSSDV8SI_MASKZ, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v8si_mask,
"__builtin_ia32_vpdpbssds_v8si_mask", IX86_BUILTIN_VPDPBSSDSV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v8si_maskz,
"__builtin_ia32_vpdpbssds_v8si_maskz", IX86_BUILTIN_VPDPBSSDSV8SI_MASKZ,
UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v8si_mask,
"__builtin_ia32_vpdpbsud_v8si_mask", IX86_BUILTIN_VPDPBSUDV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v8si_maskz,
"__builtin_ia32_vpdpbsud_v8si_maskz", IX86_BUILTIN_VPDPBSUDV8SI_MASKZ, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v8si_mask,
"__builtin_ia32_vpdpbsuds_v8si_mask", IX86_BUILTIN_VPDPBSUDSV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v8si_maskz,
"__builtin_ia32_vpdpbsuds_v8si_maskz", IX86_BUILTIN_VPDPBSUDSV8SI_MASKZ,
UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v8si_mask,
"__builtin_ia32_vpdpbuud_v8si_mask", IX86_BUILTIN_VPDPBUUDV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v8si_maskz,
"__builtin_ia32_vpdpbuud_v8si_maskz", IX86_BUILTIN_VPDPBUUDV8SI_MASKZ, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v8si_mask,
"__builtin_ia32_vpdpbuuds_v8si_mask", IX86_BUILTIN_VPDPBUUDSV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v8si_maskz,
"__builtin_ia32_vpdpbuuds_v8si_maskz", IX86_BUILTIN_VPDPBUUDSV8SI_MASKZ,
UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v4si_mask,
"__builtin_ia32_vpdpbssd_v4si_mask", IX86_BUILTIN_VPDPBSSDV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v4si_maskz,
"__builtin_ia32_vpdpbssd_v4si_maskz", IX86_BUILTIN_VPDPBSSDV4SI_MASKZ, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v4si_mask,
"__builtin_ia32_vpdpbssds_v4si_mask", IX86_BUILTIN_VPDPBSSDSV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v4si_maskz,
"__builtin_ia32_vpdpbssds_v4si_maskz", IX86_BUILTIN_VPDPBSSDSV4SI_MASKZ,
UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v4si_mask,
"__builtin_ia32_vpdpbsud_v4si_mask", IX86_BUILTIN_VPDPBSUDV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v4si_maskz,
"__builtin_ia32_vpdpbsud_v4si_maskz", IX86_BUILTIN_VPDPBSUDV4SI_MASKZ, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v4si_mask,
"__builtin_ia32_vpdpbsuds_v4si_mask", IX86_BUILTIN_VPDPBSUDSV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v4si_maskz,
"__builtin_ia32_vpdpbsuds_v4si_maskz", IX86_BUILTIN_VPDPBSUDSV4SI_MASKZ,
UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v4si_mask,
"__builtin_ia32_vpdpbuud_v4si_mask", IX86_BUILTIN_VPDPBUUDV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v4si_maskz,
"__builtin_ia32_vpdpbuud_v4si_maskz", IX86_BUILTIN_VPDPBUUDV4SI_MASKZ, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v4si_mask,
"__builtin_ia32_vpdpbuuds_v4si_mask", IX86_BUILTIN_VPDPBUUDSV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v4si_maskz,
"__builtin_ia32_vpdpbuuds_v4si_maskz", IX86_BUILTIN_VPDPBUUDSV4SI_MASKZ,
UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v16si,
"__builtin_ia32_vpdpwsud512", IX86_BUILTIN_VPDPWSUDV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v16si,
"__builtin_ia32_vpdpwsuds512", IX86_BUILTIN_VPDPWSUDSV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v16si,
"__builtin_ia32_vpdpwusd512", IX86_BUILTIN_VPDPWUSDV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v16si,
"__builtin_ia32_vpdpwusds512", IX86_BUILTIN_VPDPWUSDSV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v16si,
"__builtin_ia32_vpdpwuud512", IX86_BUILTIN_VPDPWUUDV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v16si,
"__builtin_ia32_vpdpwuuds512", IX86_BUILTIN_VPDPWUUDSV16SI, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v16si_mask,
"__builtin_ia32_vpdpwsud_v16si_mask", IX86_BUILTIN_VPDPWSUDV16SI_MASK, UNKNOWN,
(int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v16si_maskz,
"__builtin_ia32_vpdpwsud_v16si_maskz", IX86_BUILTIN_VPDPWSUDV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v16si_mask,
"__builtin_ia32_vpdpwsuds_v16si_mask", IX86_BUILTIN_VPDPWSUDSV16SI_MASK,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v16si_maskz,
"__builtin_ia32_vpdpwsuds_v16si_maskz", IX86_BUILTIN_VPDPWSUDSV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v16si_mask,
"__builtin_ia32_vpdpwusd_v16si_mask", IX86_BUILTIN_VPDPWUSDV16SI_MASK, UNKNOWN,
(int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v16si_maskz,
"__builtin_ia32_vpdpwusd_v16si_maskz", IX86_BUILTIN_VPDPWUSDV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v16si_mask,
"__builtin_ia32_vpdpwusds_v16si_mask", IX86_BUILTIN_VPDPWUSDSV16SI_MASK,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v16si_maskz,
"__builtin_ia32_vpdpwusds_v16si_maskz", IX86_BUILTIN_VPDPWUSDSV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v16si_mask,
"__builtin_ia32_vpdpwuud_v16si_mask", IX86_BUILTIN_VPDPWUUDV16SI_MASK, UNKNOWN,
(int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v16si_maskz,
"__builtin_ia32_vpdpwuud_v16si_maskz", IX86_BUILTIN_VPDPWUUDV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v16si_mask,
"__builtin_ia32_vpdpwuuds_v16si_mask", IX86_BUILTIN_VPDPWUUDSV16SI_MASK,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v16si_maskz,
"__builtin_ia32_vpdpwuuds_v16si_maskz", IX86_BUILTIN_VPDPWUUDSV16SI_MASKZ,
UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v8si_mask,
"__builtin_ia32_vpdpwsud_v8si_mask", IX86_BUILTIN_VPDPWSUDV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v8si_maskz,
"__builtin_ia32_vpdpwsud_v8si_maskz", IX86_BUILTIN_VPDPWSUDV8SI_MASKZ, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v8si_mask,
"__builtin_ia32_vpdpwsuds_v8si_mask", IX86_BUILTIN_VPDPWSUDSV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v8si_maskz,
"__builtin_ia32_vpdpwsuds_v8si_maskz", IX86_BUILTIN_VPDPWSUDSV8SI_MASKZ,
UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v8si_mask,
"__builtin_ia32_vpdpwusd_v8si_mask", IX86_BUILTIN_VPDPWUSDV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v8si_maskz,
"__builtin_ia32_vpdpwusd_v8si_maskz", IX86_BUILTIN_VPDPWUSDV8SI_MASKZ, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v8si_mask,
"__builtin_ia32_vpdpwusds_v8si_mask", IX86_BUILTIN_VPDPWUSDSV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v8si_maskz,
"__builtin_ia32_vpdpwusds_v8si_maskz", IX86_BUILTIN_VPDPWUSDSV8SI_MASKZ,
UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v8si_mask,
"__builtin_ia32_vpdpwuud_v8si_mask", IX86_BUILTIN_VPDPWUUDV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v8si_maskz,
"__builtin_ia32_vpdpwuud_v8si_maskz", IX86_BUILTIN_VPDPWUUDV8SI_MASKZ, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v8si_mask,
"__builtin_ia32_vpdpwuuds_v8si_mask", IX86_BUILTIN_VPDPWUUDSV8SI_MASK, UNKNOWN,
(int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v8si_maskz,
"__builtin_ia32_vpdpwuuds_v8si_maskz", IX86_BUILTIN_VPDPWUUDSV8SI_MASKZ,
UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v4si_mask,
"__builtin_ia32_vpdpwsud_v4si_mask", IX86_BUILTIN_VPDPWSUDV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v4si_maskz,
"__builtin_ia32_vpdpwsud_v4si_maskz", IX86_BUILTIN_VPDPWSUDV4SI_MASKZ, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v4si_mask,
"__builtin_ia32_vpdpwsuds_v4si_mask", IX86_BUILTIN_VPDPWSUDSV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v4si_maskz,
"__builtin_ia32_vpdpwsuds_v4si_maskz", IX86_BUILTIN_VPDPWSUDSV4SI_MASKZ,
UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v4si_mask,
"__builtin_ia32_vpdpwusd_v4si_mask", IX86_BUILTIN_VPDPWUSDV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v4si_maskz,
"__builtin_ia32_vpdpwusd_v4si_maskz", IX86_BUILTIN_VPDPWUSDV4SI_MASKZ, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v4si_mask,
"__builtin_ia32_vpdpwusds_v4si_mask", IX86_BUILTIN_VPDPWUSDSV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v4si_maskz,
"__builtin_ia32_vpdpwusds_v4si_maskz", IX86_BUILTIN_VPDPWUSDSV4SI_MASKZ,
UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v4si_mask,
"__builtin_ia32_vpdpwuud_v4si_mask", IX86_BUILTIN_VPDPWUUDV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v4si_maskz,
"__builtin_ia32_vpdpwuud_v4si_maskz", IX86_BUILTIN_VPDPWUUDV4SI_MASKZ, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v4si_mask,
"__builtin_ia32_vpdpwuuds_v4si_mask", IX86_BUILTIN_VPDPWUUDSV4SI_MASK, UNKNOWN,
(int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v4si_maskz,
"__builtin_ia32_vpdpwuuds_v4si_maskz", IX86_BUILTIN_VPDPWUUDSV4SI_MASKZ,
UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssd_v16si, "__builtin_ia32_vpdpbssd512",
IX86_BUILTIN_VPDPBSSDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssds_v16si, "__builtin_ia32_vpdpbssds512",
IX86_BUILTIN_VPDPBSSDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsud_v16si, "__builtin_ia32_vpdpbsud512",
IX86_BUILTIN_VPDPBSUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsuds_v16si, "__builtin_ia32_vpdpbsuds512",
IX86_BUILTIN_VPDPBSUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuud_v16si, "__builtin_ia32_vpdpbuud512",
IX86_BUILTIN_VPDPBUUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuuds_v16si, "__builtin_ia32_vpdpbuuds512",
IX86_BUILTIN_VPDPBUUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssd_v16si_mask, "__builtin_ia32_vpdpbssd_v16si_mask",
IX86_BUILTIN_VPDPBSSDV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssd_v16si_maskz, "__builtin_ia32_vpdpbssd_v16si_maskz",
IX86_BUILTIN_VPDPBSSDV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssds_v16si_mask, "__builtin_ia32_vpdpbssds_v16si_mask",
IX86_BUILTIN_VPDPBSSDSV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssds_v16si_maskz, "__builtin_ia32_vpdpbssds_v16si_maskz",
IX86_BUILTIN_VPDPBSSDSV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsud_v16si_mask, "__builtin_ia32_vpdpbsud_v16si_mask",
IX86_BUILTIN_VPDPBSUDV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsud_v16si_maskz, "__builtin_ia32_vpdpbsud_v16si_maskz",
IX86_BUILTIN_VPDPBSUDV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsuds_v16si_mask, "__builtin_ia32_vpdpbsuds_v16si_mask",
IX86_BUILTIN_VPDPBSUDSV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsuds_v16si_maskz, "__builtin_ia32_vpdpbsuds_v16si_maskz",
IX86_BUILTIN_VPDPBSUDSV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuud_v16si_mask, "__builtin_ia32_vpdpbuud_v16si_mask",
IX86_BUILTIN_VPDPBUUDV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuud_v16si_maskz, "__builtin_ia32_vpdpbuud_v16si_maskz",
IX86_BUILTIN_VPDPBUUDV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuuds_v16si_mask, "__builtin_ia32_vpdpbuuds_v16si_mask",
IX86_BUILTIN_VPDPBUUDSV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuuds_v16si_maskz, "__builtin_ia32_vpdpbuuds_v16si_maskz",
IX86_BUILTIN_VPDPBUUDSV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssd_v8si_mask, "__builtin_ia32_vpdpbssd_v8si_mask",
IX86_BUILTIN_VPDPBSSDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssd_v8si_maskz, "__builtin_ia32_vpdpbssd_v8si_maskz",
IX86_BUILTIN_VPDPBSSDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssds_v8si_mask, "__builtin_ia32_vpdpbssds_v8si_mask",
IX86_BUILTIN_VPDPBSSDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssds_v8si_maskz, "__builtin_ia32_vpdpbssds_v8si_maskz",
IX86_BUILTIN_VPDPBSSDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsud_v8si_mask, "__builtin_ia32_vpdpbsud_v8si_mask",
IX86_BUILTIN_VPDPBSUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsud_v8si_maskz, "__builtin_ia32_vpdpbsud_v8si_maskz",
IX86_BUILTIN_VPDPBSUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsuds_v8si_mask, "__builtin_ia32_vpdpbsuds_v8si_mask",
IX86_BUILTIN_VPDPBSUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsuds_v8si_maskz, "__builtin_ia32_vpdpbsuds_v8si_maskz",
IX86_BUILTIN_VPDPBSUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuud_v8si_mask, "__builtin_ia32_vpdpbuud_v8si_mask",
IX86_BUILTIN_VPDPBUUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuud_v8si_maskz, "__builtin_ia32_vpdpbuud_v8si_maskz",
IX86_BUILTIN_VPDPBUUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuuds_v8si_mask, "__builtin_ia32_vpdpbuuds_v8si_mask",
IX86_BUILTIN_VPDPBUUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuuds_v8si_maskz, "__builtin_ia32_vpdpbuuds_v8si_maskz",
IX86_BUILTIN_VPDPBUUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssd_v4si_mask, "__builtin_ia32_vpdpbssd_v4si_mask",
IX86_BUILTIN_VPDPBSSDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssd_v4si_maskz, "__builtin_ia32_vpdpbssd_v4si_maskz",
IX86_BUILTIN_VPDPBSSDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssds_v4si_mask, "__builtin_ia32_vpdpbssds_v4si_mask",
IX86_BUILTIN_VPDPBSSDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbssds_v4si_maskz, "__builtin_ia32_vpdpbssds_v4si_maskz",
IX86_BUILTIN_VPDPBSSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsud_v4si_mask, "__builtin_ia32_vpdpbsud_v4si_mask",
IX86_BUILTIN_VPDPBSUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsud_v4si_maskz, "__builtin_ia32_vpdpbsud_v4si_maskz",
IX86_BUILTIN_VPDPBSUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsuds_v4si_mask, "__builtin_ia32_vpdpbsuds_v4si_mask",
IX86_BUILTIN_VPDPBSUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbsuds_v4si_maskz, "__builtin_ia32_vpdpbsuds_v4si_maskz",
IX86_BUILTIN_VPDPBSUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuud_v4si_mask, "__builtin_ia32_vpdpbuud_v4si_mask",
IX86_BUILTIN_VPDPBUUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuud_v4si_maskz, "__builtin_ia32_vpdpbuud_v4si_maskz",
IX86_BUILTIN_VPDPBUUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuuds_v4si_mask, "__builtin_ia32_vpdpbuuds_v4si_mask",
IX86_BUILTIN_VPDPBUUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpbuuds_v4si_maskz, "__builtin_ia32_vpdpbuuds_v4si_maskz",
IX86_BUILTIN_VPDPBUUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsud_v16si, "__builtin_ia32_vpdpwsud512",
IX86_BUILTIN_VPDPWSUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsuds_v16si, "__builtin_ia32_vpdpwsuds512",
IX86_BUILTIN_VPDPWSUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusd_v16si, "__builtin_ia32_vpdpwusd512",
IX86_BUILTIN_VPDPWUSDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusds_v16si, "__builtin_ia32_vpdpwusds512",
IX86_BUILTIN_VPDPWUSDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuud_v16si, "__builtin_ia32_vpdpwuud512",
IX86_BUILTIN_VPDPWUUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuuds_v16si, "__builtin_ia32_vpdpwuuds512",
IX86_BUILTIN_VPDPWUUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsud_v16si_mask, "__builtin_ia32_vpdpwsud_v16si_mask",
IX86_BUILTIN_VPDPWSUDV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsud_v16si_maskz, "__builtin_ia32_vpdpwsud_v16si_maskz",
IX86_BUILTIN_VPDPWSUDV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsuds_v16si_mask, "__builtin_ia32_vpdpwsuds_v16si_mask",
IX86_BUILTIN_VPDPWSUDSV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsuds_v16si_maskz, "__builtin_ia32_vpdpwsuds_v16si_maskz",
IX86_BUILTIN_VPDPWSUDSV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusd_v16si_mask, "__builtin_ia32_vpdpwusd_v16si_mask",
IX86_BUILTIN_VPDPWUSDV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusd_v16si_maskz, "__builtin_ia32_vpdpwusd_v16si_maskz",
IX86_BUILTIN_VPDPWUSDV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusds_v16si_mask, "__builtin_ia32_vpdpwusds_v16si_mask",
IX86_BUILTIN_VPDPWUSDSV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusds_v16si_maskz, "__builtin_ia32_vpdpwusds_v16si_maskz",
IX86_BUILTIN_VPDPWUSDSV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuud_v16si_mask, "__builtin_ia32_vpdpwuud_v16si_mask",
IX86_BUILTIN_VPDPWUUDV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuud_v16si_maskz, "__builtin_ia32_vpdpwuud_v16si_maskz",
IX86_BUILTIN_VPDPWUUDV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuuds_v16si_mask, "__builtin_ia32_vpdpwuuds_v16si_mask",
IX86_BUILTIN_VPDPWUUDSV16SI_MASK, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuuds_v16si_maskz, "__builtin_ia32_vpdpwuuds_v16si_maskz",
IX86_BUILTIN_VPDPWUUDSV16SI_MASKZ, UNKNOWN, (int)
V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsud_v8si_mask, "__builtin_ia32_vpdpwsud_v8si_mask",
IX86_BUILTIN_VPDPWSUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsud_v8si_maskz, "__builtin_ia32_vpdpwsud_v8si_maskz",
IX86_BUILTIN_VPDPWSUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsuds_v8si_mask, "__builtin_ia32_vpdpwsuds_v8si_mask",
IX86_BUILTIN_VPDPWSUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsuds_v8si_maskz, "__builtin_ia32_vpdpwsuds_v8si_maskz",
IX86_BUILTIN_VPDPWSUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusd_v8si_mask, "__builtin_ia32_vpdpwusd_v8si_mask",
IX86_BUILTIN_VPDPWUSDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusd_v8si_maskz, "__builtin_ia32_vpdpwusd_v8si_maskz",
IX86_BUILTIN_VPDPWUSDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusds_v8si_mask, "__builtin_ia32_vpdpwusds_v8si_mask",
IX86_BUILTIN_VPDPWUSDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusds_v8si_maskz, "__builtin_ia32_vpdpwusds_v8si_maskz",
IX86_BUILTIN_VPDPWUSDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuud_v8si_mask, "__builtin_ia32_vpdpwuud_v8si_mask",
IX86_BUILTIN_VPDPWUUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuud_v8si_maskz, "__builtin_ia32_vpdpwuud_v8si_maskz",
IX86_BUILTIN_VPDPWUUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuuds_v8si_mask, "__builtin_ia32_vpdpwuuds_v8si_mask",
IX86_BUILTIN_VPDPWUUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuuds_v8si_maskz, "__builtin_ia32_vpdpwuuds_v8si_maskz",
IX86_BUILTIN_VPDPWUUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsud_v4si_mask, "__builtin_ia32_vpdpwsud_v4si_mask",
IX86_BUILTIN_VPDPWSUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsud_v4si_maskz, "__builtin_ia32_vpdpwsud_v4si_maskz",
IX86_BUILTIN_VPDPWSUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsuds_v4si_mask, "__builtin_ia32_vpdpwsuds_v4si_mask",
IX86_BUILTIN_VPDPWSUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwsuds_v4si_maskz, "__builtin_ia32_vpdpwsuds_v4si_maskz",
IX86_BUILTIN_VPDPWSUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusd_v4si_mask, "__builtin_ia32_vpdpwusd_v4si_mask",
IX86_BUILTIN_VPDPWUSDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusd_v4si_maskz, "__builtin_ia32_vpdpwusd_v4si_maskz",
IX86_BUILTIN_VPDPWUSDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusds_v4si_mask, "__builtin_ia32_vpdpwusds_v4si_mask",
IX86_BUILTIN_VPDPWUSDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwusds_v4si_maskz, "__builtin_ia32_vpdpwusds_v4si_maskz",
IX86_BUILTIN_VPDPWUSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuud_v4si_mask, "__builtin_ia32_vpdpwuud_v4si_mask",
IX86_BUILTIN_VPDPWUUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuud_v4si_maskz, "__builtin_ia32_vpdpwuud_v4si_maskz",
IX86_BUILTIN_VPDPWUUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuuds_v4si_mask, "__builtin_ia32_vpdpwuuds_v4si_mask",
IX86_BUILTIN_VPDPWUUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vpdpwuuds_v4si_maskz, "__builtin_ia32_vpdpwuuds_v4si_maskz",
IX86_BUILTIN_VPDPWUUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vdpphps_v16sf_mask,
"__builtin_ia32_vdpphps512_mask", IX86_BUILTIN_VDPPHPS512_MASK, UNKNOWN, (int)
V16SF_FTYPE_V16SF_V16SF_V16SF_UHI)
BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vdpphps_v16sf_maskz,
"__builtin_ia32_vdpphps512_maskz", IX86_BUILTIN_VDPPHPS512_MASKZ, UNKNOWN,
(int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI)
BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vdpphps_v8sf_mask,
"__builtin_ia32_vdpphps256_mask", IX86_BUILTIN_VDPPHPS256_MASK, UNKNOWN, (int)
V8SF_FTYPE_V8SF_V8SF_V8SF_UQI)
@@ -3148,51 +3148,51 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_avx10_2_mpsadbw, "__builtin_ia32_mp
BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_mpsadbw_mask,
"__builtin_ia32_mpsadbw512_mask", IX86_BUILTIN_VMPSADBW_V32HI_MASK, UNKNOWN,
(int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_USI)
BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx2_mpsadbw_mask,
"__builtin_ia32_mpsadbw256_mask", IX86_BUILTIN_VMPSADBW_V16HI_MASK, UNKNOWN,
(int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_UHI)
BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_sse4_1_mpsadbw_mask,
"__builtin_ia32_mpsadbw128_mask", IX86_BUILTIN_VMPSADBW_V8HI_MASK, UNKNOWN,
(int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvt2ps2phx_v16hf_mask,
"__builtin_ia32_vcvt2ps2phx256_mask", IX86_BUILTIN_VCVT2PS2PHX_V16HF_MASK,
UNKNOWN, (int) V16HF_FTYPE_V8SF_V8SF_V16HF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvt2ps2phx_v8hf_mask,
"__builtin_ia32_vcvt2ps2phx128_mask", IX86_BUILTIN_VCVT2PS2PHX_V8HF_MASK,
UNKNOWN, (int) V8HF_FTYPE_V4SF_V4SF_V8HF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8v8hf,
"__builtin_ia32_vcvtbiasph2bf8128", IX86_BUILTIN_VCVTBIASPH2BF8128, UNKNOWN,
(int) V16QI_FTYPE_V16QI_V8HF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8v8hf_mask,
"__builtin_ia32_vcvtbiasph2bf8128_mask", IX86_BUILTIN_VCVTBIASPH2BF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8v16hf_mask,
"__builtin_ia32_vcvtbiasph2bf8256_mask", IX86_BUILTIN_VCVTBIASPH2BF8256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8v32hf_mask,
"__builtin_ia32_vcvtbiasph2bf8512_mask", IX86_BUILTIN_VCVTBIASPH2BF8512_MASK,
UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8sv8hf,
"__builtin_ia32_vcvtbiasph2bf8s128", IX86_BUILTIN_VCVTBIASPH2BF8S128, UNKNOWN,
(int) V16QI_FTYPE_V16QI_V8HF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8sv8hf_mask,
"__builtin_ia32_vcvtbiasph2bf8s128_mask", IX86_BUILTIN_VCVTBIASPH2BF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8sv16hf_mask,
"__builtin_ia32_vcvtbiasph2bf8s256_mask", IX86_BUILTIN_VCVTBIASPH2BF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8sv32hf_mask,
"__builtin_ia32_vcvtbiasph2bf8s512_mask", IX86_BUILTIN_VCVTBIASPH2BF8S512_MASK,
UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8v8hf,
"__builtin_ia32_vcvtbiasph2hf8128", IX86_BUILTIN_VCVTBIASPH2HF8128, UNKNOWN,
(int) V16QI_FTYPE_V16QI_V8HF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8v8hf_mask,
"__builtin_ia32_vcvtbiasph2hf8128_mask", IX86_BUILTIN_VCVTBIASPH2HF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8v16hf_mask,
"__builtin_ia32_vcvtbiasph2hf8256_mask", IX86_BUILTIN_VCVTBIASPH2HF8256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8v32hf_mask,
"__builtin_ia32_vcvtbiasph2hf8512_mask", IX86_BUILTIN_VCVTBIASPH2HF8512_MASK,
UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8sv8hf,
"__builtin_ia32_vcvtbiasph2hf8s128", IX86_BUILTIN_VCVTBIASPH2HF8S128, UNKNOWN,
(int) V16QI_FTYPE_V16QI_V8HF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8sv8hf_mask,
"__builtin_ia32_vcvtbiasph2hf8s128_mask", IX86_BUILTIN_VCVTBIASPH2HF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8sv16hf_mask,
"__builtin_ia32_vcvtbiasph2hf8s256_mask", IX86_BUILTIN_VCVTBIASPH2HF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8sv32hf_mask,
"__builtin_ia32_vcvtbiasph2hf8s512_mask", IX86_BUILTIN_VCVTBIASPH2HF8S512_MASK,
UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8v8hf_mask,
"__builtin_ia32_vcvt2ph2bf8128_mask", IX86_BUILTIN_VCVT2PH2BF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8v16hf_mask,
"__builtin_ia32_vcvt2ph2bf8256_mask", IX86_BUILTIN_VCVT2PH2BF8256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8v32hf_mask,
"__builtin_ia32_vcvt2ph2bf8512_mask", IX86_BUILTIN_VCVT2PH2BF8512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8sv8hf_mask,
"__builtin_ia32_vcvt2ph2bf8s128_mask", IX86_BUILTIN_VCVT2PH2BF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8sv16hf_mask,
"__builtin_ia32_vcvt2ph2bf8s256_mask", IX86_BUILTIN_VCVT2PH2BF8S256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8sv32hf_mask,
"__builtin_ia32_vcvt2ph2bf8s512_mask", IX86_BUILTIN_VCVT2PH2BF8S512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8v8hf_mask,
"__builtin_ia32_vcvt2ph2hf8128_mask", IX86_BUILTIN_VCVT2PH2HF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8v16hf_mask,
"__builtin_ia32_vcvt2ph2hf8256_mask", IX86_BUILTIN_VCVT2PH2HF8256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8v32hf_mask,
"__builtin_ia32_vcvt2ph2hf8512_mask", IX86_BUILTIN_VCVT2PH2HF8512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8sv8hf_mask,
"__builtin_ia32_vcvt2ph2hf8s128_mask", IX86_BUILTIN_VCVT2PH2HF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8sv16hf_mask,
"__builtin_ia32_vcvt2ph2hf8s256_mask", IX86_BUILTIN_VCVT2PH2HF8S256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8sv32hf_mask,
"__builtin_ia32_vcvt2ph2hf8s512_mask", IX86_BUILTIN_VCVT2PH2HF8S512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8v8hf_mask,
"__builtin_ia32_vcvtph2bf8128_mask", IX86_BUILTIN_VCVTPH2BF8128_MASK, UNKNOWN,
(int) V16QI_FTYPE_V8HF_V16QI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8v16hf_mask,
"__builtin_ia32_vcvtph2bf8256_mask", IX86_BUILTIN_VCVTPH2BF8256_MASK, UNKNOWN,
(int) V16QI_FTYPE_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8v32hf_mask,
"__builtin_ia32_vcvtph2bf8512_mask", IX86_BUILTIN_VCVTPH2BF8512_MASK, UNKNOWN,
(int) V32QI_FTYPE_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8sv8hf_mask,
"__builtin_ia32_vcvtph2bf8s128_mask", IX86_BUILTIN_VCVTPH2BF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8sv16hf_mask,
"__builtin_ia32_vcvtph2bf8s256_mask", IX86_BUILTIN_VCVTPH2BF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8sv32hf_mask,
"__builtin_ia32_vcvtph2bf8s512_mask", IX86_BUILTIN_VCVTPH2BF8S512_MASK,
UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8v8hf_mask,
"__builtin_ia32_vcvtph2hf8128_mask", IX86_BUILTIN_VCVTPH2HF8128_MASK, UNKNOWN,
(int) V16QI_FTYPE_V8HF_V16QI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8v16hf_mask,
"__builtin_ia32_vcvtph2hf8256_mask", IX86_BUILTIN_VCVTPH2HF8256_MASK, UNKNOWN,
(int) V16QI_FTYPE_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8v32hf_mask,
"__builtin_ia32_vcvtph2hf8512_mask", IX86_BUILTIN_VCVTPH2HF8512_MASK, UNKNOWN,
(int) V32QI_FTYPE_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8sv8hf_mask,
"__builtin_ia32_vcvtph2hf8s128_mask", IX86_BUILTIN_VCVTPH2HF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8sv16hf_mask,
"__builtin_ia32_vcvtph2hf8s256_mask", IX86_BUILTIN_VCVTPH2HF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8sv32hf_mask,
"__builtin_ia32_vcvtph2hf8s512_mask", IX86_BUILTIN_VCVTPH2HF8S512_MASK,
UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvthf82phv8hf_mask,
"__builtin_ia32_vcvthf82ph128_mask", IX86_BUILTIN_VCVTHF82PH128_MASK, UNKNOWN,
(int) V8HF_FTYPE_V16QI_V8HF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvthf82phv16hf_mask,
"__builtin_ia32_vcvthf82ph256_mask", IX86_BUILTIN_VCVTHF82PH256_MASK, UNKNOWN,
(int) V16HF_FTYPE_V16QI_V16HF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvthf82phv32hf_mask,
"__builtin_ia32_vcvthf82ph512_mask", IX86_BUILTIN_VCVTHF82PH512_MASK, UNKNOWN,
(int) V32HF_FTYPE_V32QI_V32HF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_avx10_2_cvt2ps2phx_v16hf_mask, "__builtin_ia32_vcvt2ps2phx256_mask",
IX86_BUILTIN_VCVT2PS2PHX_V16HF_MASK, UNKNOWN, (int)
V16HF_FTYPE_V8SF_V8SF_V16HF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_avx10_2_cvt2ps2phx_v8hf_mask, "__builtin_ia32_vcvt2ps2phx128_mask",
IX86_BUILTIN_VCVT2PS2PHX_V8HF_MASK, UNKNOWN, (int)
V8HF_FTYPE_V4SF_V4SF_V8HF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2bf8v8hf, "__builtin_ia32_vcvtbiasph2bf8128",
IX86_BUILTIN_VCVTBIASPH2BF8128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2bf8v8hf_mask, "__builtin_ia32_vcvtbiasph2bf8128_mask",
IX86_BUILTIN_VCVTBIASPH2BF8128_MASK, UNKNOWN, (int)
V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2bf8v16hf_mask, "__builtin_ia32_vcvtbiasph2bf8256_mask",
IX86_BUILTIN_VCVTBIASPH2BF8256_MASK, UNKNOWN, (int)
V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2bf8v32hf_mask, "__builtin_ia32_vcvtbiasph2bf8512_mask",
IX86_BUILTIN_VCVTBIASPH2BF8512_MASK, UNKNOWN, (int)
V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2bf8sv8hf, "__builtin_ia32_vcvtbiasph2bf8s128",
IX86_BUILTIN_VCVTBIASPH2BF8S128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2bf8sv8hf_mask, "__builtin_ia32_vcvtbiasph2bf8s128_mask",
IX86_BUILTIN_VCVTBIASPH2BF8S128_MASK, UNKNOWN, (int)
V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2bf8sv16hf_mask, "__builtin_ia32_vcvtbiasph2bf8s256_mask",
IX86_BUILTIN_VCVTBIASPH2BF8S256_MASK, UNKNOWN, (int)
V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2bf8sv32hf_mask, "__builtin_ia32_vcvtbiasph2bf8s512_mask",
IX86_BUILTIN_VCVTBIASPH2BF8S512_MASK, UNKNOWN, (int)
V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2hf8v8hf, "__builtin_ia32_vcvtbiasph2hf8128",
IX86_BUILTIN_VCVTBIASPH2HF8128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2hf8v8hf_mask, "__builtin_ia32_vcvtbiasph2hf8128_mask",
IX86_BUILTIN_VCVTBIASPH2HF8128_MASK, UNKNOWN, (int)
V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2hf8v16hf_mask, "__builtin_ia32_vcvtbiasph2hf8256_mask",
IX86_BUILTIN_VCVTBIASPH2HF8256_MASK, UNKNOWN, (int)
V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2hf8v32hf_mask, "__builtin_ia32_vcvtbiasph2hf8512_mask",
IX86_BUILTIN_VCVTBIASPH2HF8512_MASK, UNKNOWN, (int)
V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2hf8sv8hf, "__builtin_ia32_vcvtbiasph2hf8s128",
IX86_BUILTIN_VCVTBIASPH2HF8S128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2hf8sv8hf_mask, "__builtin_ia32_vcvtbiasph2hf8s128_mask",
IX86_BUILTIN_VCVTBIASPH2HF8S128_MASK, UNKNOWN, (int)
V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2hf8sv16hf_mask, "__builtin_ia32_vcvtbiasph2hf8s256_mask",
IX86_BUILTIN_VCVTBIASPH2HF8S256_MASK, UNKNOWN, (int)
V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtbiasph2hf8sv32hf_mask, "__builtin_ia32_vcvtbiasph2hf8s512_mask",
IX86_BUILTIN_VCVTBIASPH2HF8S512_MASK, UNKNOWN, (int)
V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2bf8v8hf_mask, "__builtin_ia32_vcvt2ph2bf8128_mask",
IX86_BUILTIN_VCVT2PH2BF8128_MASK, UNKNOWN, (int)
V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2bf8v16hf_mask, "__builtin_ia32_vcvt2ph2bf8256_mask",
IX86_BUILTIN_VCVT2PH2BF8256_MASK, UNKNOWN, (int)
V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2bf8v32hf_mask, "__builtin_ia32_vcvt2ph2bf8512_mask",
IX86_BUILTIN_VCVT2PH2BF8512_MASK, UNKNOWN, (int)
V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2bf8sv8hf_mask, "__builtin_ia32_vcvt2ph2bf8s128_mask",
IX86_BUILTIN_VCVT2PH2BF8S128_MASK, UNKNOWN, (int)
V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2bf8sv16hf_mask, "__builtin_ia32_vcvt2ph2bf8s256_mask",
IX86_BUILTIN_VCVT2PH2BF8S256_MASK, UNKNOWN, (int)
V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2bf8sv32hf_mask, "__builtin_ia32_vcvt2ph2bf8s512_mask",
IX86_BUILTIN_VCVT2PH2BF8S512_MASK, UNKNOWN, (int)
V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2hf8v8hf_mask, "__builtin_ia32_vcvt2ph2hf8128_mask",
IX86_BUILTIN_VCVT2PH2HF8128_MASK, UNKNOWN, (int)
V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2hf8v16hf_mask, "__builtin_ia32_vcvt2ph2hf8256_mask",
IX86_BUILTIN_VCVT2PH2HF8256_MASK, UNKNOWN, (int)
V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2hf8v32hf_mask, "__builtin_ia32_vcvt2ph2hf8512_mask",
IX86_BUILTIN_VCVT2PH2HF8512_MASK, UNKNOWN, (int)
V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2hf8sv8hf_mask, "__builtin_ia32_vcvt2ph2hf8s128_mask",
IX86_BUILTIN_VCVT2PH2HF8S128_MASK, UNKNOWN, (int)
V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2hf8sv16hf_mask, "__builtin_ia32_vcvt2ph2hf8s256_mask",
IX86_BUILTIN_VCVT2PH2HF8S256_MASK, UNKNOWN, (int)
V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvt2ph2hf8sv32hf_mask, "__builtin_ia32_vcvt2ph2hf8s512_mask",
IX86_BUILTIN_VCVT2PH2HF8S512_MASK, UNKNOWN, (int)
V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2bf8v8hf_mask, "__builtin_ia32_vcvtph2bf8128_mask",
IX86_BUILTIN_VCVTPH2BF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2bf8v16hf_mask, "__builtin_ia32_vcvtph2bf8256_mask",
IX86_BUILTIN_VCVTPH2BF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2bf8v32hf_mask, "__builtin_ia32_vcvtph2bf8512_mask",
IX86_BUILTIN_VCVTPH2BF8512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2bf8sv8hf_mask, "__builtin_ia32_vcvtph2bf8s128_mask",
IX86_BUILTIN_VCVTPH2BF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2bf8sv16hf_mask, "__builtin_ia32_vcvtph2bf8s256_mask",
IX86_BUILTIN_VCVTPH2BF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2bf8sv32hf_mask, "__builtin_ia32_vcvtph2bf8s512_mask",
IX86_BUILTIN_VCVTPH2BF8S512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2hf8v8hf_mask, "__builtin_ia32_vcvtph2hf8128_mask",
IX86_BUILTIN_VCVTPH2HF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2hf8v16hf_mask, "__builtin_ia32_vcvtph2hf8256_mask",
IX86_BUILTIN_VCVTPH2HF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2hf8v32hf_mask, "__builtin_ia32_vcvtph2hf8512_mask",
IX86_BUILTIN_VCVTPH2HF8512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2hf8sv8hf_mask, "__builtin_ia32_vcvtph2hf8s128_mask",
IX86_BUILTIN_VCVTPH2HF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2hf8sv16hf_mask, "__builtin_ia32_vcvtph2hf8s256_mask",
IX86_BUILTIN_VCVTPH2HF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvtph2hf8sv32hf_mask, "__builtin_ia32_vcvtph2hf8s512_mask",
IX86_BUILTIN_VCVTPH2HF8S512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvthf82phv8hf_mask, "__builtin_ia32_vcvthf82ph128_mask",
IX86_BUILTIN_VCVTHF82PH128_MASK, UNKNOWN, (int) V8HF_FTYPE_V16QI_V8HF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvthf82phv16hf_mask, "__builtin_ia32_vcvthf82ph256_mask",
IX86_BUILTIN_VCVTHF82PH256_MASK, UNKNOWN, (int) V16HF_FTYPE_V16QI_V16HF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_vcvthf82phv32hf_mask, "__builtin_ia32_vcvthf82ph512_mask",
IX86_BUILTIN_VCVTHF82PH512_MASK, UNKNOWN, (int) V32HF_FTYPE_V32QI_V32HF_USI)
BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_addbf16_v32bf,
"__builtin_ia32_addbf16512", IX86_BUILTIN_ADDBF16512, UNKNOWN, (int)
V32BF_FTYPE_V32BF_V32BF)
BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_addbf16_v32bf_mask,
"__builtin_ia32_addbf16512_mask", IX86_BUILTIN_ADDBF16512_MASK, UNKNOWN, (int)
V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_addbf16_v16bf,
"__builtin_ia32_addbf16256", IX86_BUILTIN_ADDBF16256, UNKNOWN, (int)
V16BF_FTYPE_V16BF_V16BF)
@@ -3738,7 +3738,7 @@ BDESC (0, OPTION_MASK_ISA2_AVX512FP16,
CODE_FOR_avx512fp16_fmulcsh_v8hf_round, "
BDESC (0, OPTION_MASK_ISA2_AVX512FP16,
CODE_FOR_avx512fp16_fmulcsh_v8hf_mask_round,
"__builtin_ia32_vfmulcsh_mask_round", IX86_BUILTIN_VFMULCSH_MASK_ROUND,
UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI_INT)
/* AVX10.2. */
-BDESC (0, OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_avx10_2_cvt2ps2phx_v32hf_mask_round,
"__builtin_ia32_vcvt2ps2phx512_mask_round",
IX86_BUILTIN_VCVT2PS2PHX_V32HF_MASK_ROUND, UNKNOWN, (int)
V32HF_FTYPE_V16SF_V16SF_V32HF_USI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_avx10_2_cvt2ps2phx_v32hf_mask_round,
"__builtin_ia32_vcvt2ps2phx512_mask_round",
IX86_BUILTIN_VCVT2PS2PHX_V32HF_MASK_ROUND, UNKNOWN, (int)
V32HF_FTYPE_V16SF_V16SF_V32HF_USI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_avx10_2_cvtph2ibsv32hf_mask_round,
"__builtin_ia32_cvtph2ibs512_mask_round", IX86_BUILTIN_CVTPH2IBS512_MASK_ROUND,
UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_avx10_2_cvtph2iubsv32hf_mask_round,
"__builtin_ia32_cvtph2iubs512_mask_round",
IX86_BUILTIN_CVTPH2IUBS512_MASK_ROUND, UNKNOWN, (int)
V32HI_FTYPE_V32HF_V32HI_USI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2,
CODE_FOR_avx10_2_cvtps2ibsv16sf_mask_round,
"__builtin_ia32_cvtps2ibs512_mask_round", IX86_BUILTIN_CVTPS2IBS512_MASK_ROUND,
UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI_INT)
diff --git a/gcc/config/i386/i386-builtins.cc b/gcc/config/i386/i386-builtins.cc
index a34d977b757..02a44d005f5 100644
--- a/gcc/config/i386/i386-builtins.cc
+++ b/gcc/config/i386/i386-builtins.cc
@@ -284,10 +284,10 @@ def_builtin (HOST_WIDE_INT mask, HOST_WIDE_INT mask2,
|| ((mask & OPTION_MASK_ISA_MMX) != 0 && TARGET_MMX_WITH_SSE)
/* "Unified" builtin used by either AVXVNNI/AVXIFMA/AES/
AVXVNNIINT{8,16}/AMX-TILE intrinsics or AVX512VNNIVL/AVX512IFMAVL/
- VAESVL/AVX10.2/ACEv1 non-mask intrinsics should be defined
+ VAESVL/AVX10.2/ACEv1/AVX10V1AUX non-mask intrinsics should be
defined
whenever avxvnni/avxifma/aes/avxvnniint{8,16}/amx-tile or
avx512vnni && avx512vl/avx512ifma && avx512vl/vaes && avx512vl/
- avx10.2/acev1 exist. */
+ avx10.2/acev1/avx10v1aux exist. */
|| (mask2 == OPTION_MASK_ISA2_AVXVNNI)
|| (mask2 == OPTION_MASK_ISA2_AVXIFMA)
|| (mask2 == (OPTION_MASK_ISA2_AVXNECONVERT
@@ -296,6 +296,7 @@ def_builtin (HOST_WIDE_INT mask, HOST_WIDE_INT mask2,
|| ((mask2 & OPTION_MASK_ISA2_AVXVNNIINT8) != 0)
|| ((mask2 & OPTION_MASK_ISA2_AVXVNNIINT16) != 0)
|| ((mask2 & OPTION_MASK_ISA2_AMX_TILE) != 0)
+ || ((mask2 & OPTION_MASK_ISA2_AVX10_2) != 0)
|| (lang_hooks.builtin_function
== lang_hooks.builtin_function_ext_scope))
{
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 2d250fa57b2..c9e60632497 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -14992,6 +14992,9 @@ ix86_check_builtin_isa_match (unsigned int fcode,
OPTION_MASK_ISA_AES or (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA2_VAES)
OPTION_MASK_ISA2_AVX10_2 or OPTION_MASK_ISA2_AVXVNNIINT8
OPTION_MASK_ISA2_AVX10_2 or OPTION_MASK_ISA2_AVXVNNIINT16
+ OPTION_MASK_ISA2_AVX10V1AUX or OPTION_MASK_ISA2_AVXVNNIINT8
+ OPTION_MASK_ISA2_AVX10V1AUX or OPTION_MASK_ISA2_AVXVNNIINT16
+ OPTION_MASK_ISA2_AVX10V1AUX or OPTION_MASK_ISA2_AVX10_2
OPTION_MASK_ISA2_AMX_TILE or OPTION_MASK_ISA2_ACEV1
where for each such pair it is sufficient if either of the ISAs is
enabled, plus if it is ored with other options also those others.
@@ -15023,6 +15026,12 @@ ix86_check_builtin_isa_match (unsigned int fcode,
SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVXVNNIINT16, 0,
OPTION_MASK_ISA2_AVX10_2);
SHARE_BUILTIN (0, OPTION_MASK_ISA2_AMX_TILE, 0, OPTION_MASK_ISA2_ACEV1);
+ SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVXVNNIINT8, 0,
+ OPTION_MASK_ISA2_AVX10V1AUX);
+ SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVXVNNIINT16, 0,
+ OPTION_MASK_ISA2_AVX10V1AUX);
+ SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVX10_2, 0,
+ OPTION_MASK_ISA2_AVX10V1AUX);
isa = tmp_isa;
isa2 = tmp_isa2;
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 9888644ed91..82dad3d25b3 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -613,7 +613,8 @@
avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl,
avx512vl,noavx512vl,avxvnni,avxvnniint8,avx512vnnivl,avx512fp16,avxifma,
avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl,
- avx_noavx512f,avx_noavx512vl,vaes_avx512vl,noapx_nf,avx10_2"
+ avx_noavx512f,avx_noavx512vl,vaes_avx512vl,noapx_nf,avx10_2,
+ avx10v1aux"
(const_string "base"))
;; The (bounding maximum) length of an instruction immediate.
@@ -1015,6 +1016,7 @@
(eq_attr "isa" "vaes_avx512vl")
(symbol_ref "TARGET_VAES && TARGET_AVX512VL")
(eq_attr "isa" "avx10_2") (symbol_ref "TARGET_AVX10_2")
+ (eq_attr "isa" "avx10v1aux") (symbol_ref "TARGET_AVX10V1AUX")
(eq_attr "mmx_isa" "native")
(symbol_ref "!TARGET_MMX_WITH_SSE")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e4bc746dacc..16cde4c53a0 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -715,7 +715,7 @@
[V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")])
(define_mode_iterator VI4_AVX10_2
- [(V16SI "TARGET_AVX10_2") V8SI V4SI])
+ [(V16SI "TARGET_AVX10_2 || TARGET_AVX10V1AUX") V8SI V4SI])
(define_mode_iterator VI48_AVX512F_AVX512VL
[V4SI V8SI (V16SI "TARGET_AVX512F")
@@ -33073,8 +33073,8 @@
(match_operand:<ssedvecmode> 3 "register_operand")]
"TARGET_SSE2"
{
- if ((<MODE_SIZE> == 64 && TARGET_AVX10_2)
- || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2)))
+ if ((<MODE_SIZE> == 64 && (TARGET_AVX10_2 || TARGET_AVX10V1AUX))
+ || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2 ||
TARGET_AVX10V1AUX)))
{
operands[1] = lowpart_subreg (<ssedvecmode>mode,
force_reg (<MODE>mode, operands[1]),
@@ -33121,8 +33121,8 @@
(match_operand:<ssedvecmode> 3 "register_operand")]
"TARGET_SSE2"
{
- if ((<MODE_SIZE> == 64 && TARGET_AVX10_2)
- || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2)))
+ if ((<MODE_SIZE> == 64 && (TARGET_AVX10_2 || TARGET_AVX10V1AUX))
+ || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2 ||
TARGET_AVX10V1AUX)))
{
operands[1] = lowpart_subreg (<ssedvecmode>mode,
force_reg (<MODE>mode, operands[1]),
@@ -33163,17 +33163,17 @@
})
(define_insn "vpdp<vpdotprodtype>_<mode>"
- [(set (match_operand:VI4_AVX 0 "register_operand" "=x,v")
+ [(set (match_operand:VI4_AVX 0 "register_operand" "=x,v,v")
(unspec:VI4_AVX
- [(match_operand:VI4_AVX 1 "register_operand" "0,0")
- (match_operand:VI4_AVX 2 "register_operand" "x,v")
- (match_operand:VI4_AVX 3 "nonimmediate_operand" "xjm,vm")]
+ [(match_operand:VI4_AVX 1 "register_operand" "0,0,0")
+ (match_operand:VI4_AVX 2 "register_operand" "x,v,v")
+ (match_operand:VI4_AVX 3 "nonimmediate_operand" "xjm,vm,vm")]
VPDOTPROD))]
- "TARGET_AVXVNNIINT8 || TARGET_AVX10_2"
+ "TARGET_AVXVNNIINT8 || TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vpdp<vpdotprodtype>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "prefix" "maybe_evex")
- (set_attr "addr" "gpr16,*")
- (set_attr "isa" "avxvnniint8,avx10_2")])
+ (set_attr "addr" "gpr16,*,*")
+ (set_attr "isa" "avxvnniint8,avx10_2,avx10v1aux")])
(define_insn "vpdp<vpdotprodtype>_v16si"
[(set (match_operand:V16SI 0 "register_operand" "=v")
@@ -33182,7 +33182,7 @@
(match_operand:V16SI 2 "register_operand" "v")
(match_operand:V16SI 3 "nonimmediate_operand" "vm")]
VPDOTPROD))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vpdp<vpdotprodtype>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -33196,7 +33196,7 @@
VPDOTPROD)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vpdp<vpdotprodtype>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -33210,7 +33210,7 @@
VPDOTPROD)
(match_dup 5)
(match_operand:<avx512fmaskmode> 4 "register_operand")))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"operands[5] = CONST0_RTX (<MODE>mode);")
(define_insn "*vpdp<vpdotprodtype>_<mode>_maskz"
@@ -33223,7 +33223,7 @@
VPDOTPROD)
(match_operand:VI4_AVX10_2 5 "const0_operand" "C")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vpdp<vpdotprodtype>\t{%3, %2, %0%{%4%}%N5|%0%{%4%}%N5, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -33316,7 +33316,7 @@
(match_operand:<ssePSmode> 2 "<round_nimm_predicate>"
"<round_constraint>"))
(float_truncate:<ssehalfvecmode>
(match_operand:<ssePSmode> 1 "register_operand" "v"))))]
- "TARGET_AVX10_2 && <round_mode512bit_condition>"
+ "(TARGET_AVX10_2 || TARGET_AVX10V1AUX) && <round_mode512bit_condition>"
"vcvt2ps2phx\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>,
%1, %2<round_mask_op3>}")
(define_mode_attr ssebvecmode
@@ -33338,7 +33338,7 @@
[(match_operand:VHF_AVX512VL 1 "register_operand" "v")
(match_operand:VHF_AVX512VL 2 "nonimmediate_operand" "vm")]
UNSPEC_CONVERTFP8_PACK))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vcvt<convertfp8_pack>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1,
%2}"
[(set_attr "prefix" "evex")])
@@ -33367,7 +33367,7 @@
(match_operand:V8HF 2 "nonimmediate_operand")]
UNSPEC_VCVTBIASPH2FP8_PACK)
(match_dup 3)))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"operands[3] = CONST0_RTX (V8QImode);")
(define_insn "*vcvt<biasph2fp8_pack>v8hf"
@@ -33378,7 +33378,7 @@
(match_operand:V8HF 2 "nonimmediate_operand" "vm")]
UNSPEC_VCVTBIASPH2FP8_PACK)
(match_operand:V8QI 3 "const0_operand")))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vcvt<biasph2fp8_pack>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "prefix" "evex")
(set_attr "mode" "HF")])
@@ -33399,7 +33399,7 @@
(const_int 6) (const_int 7)]))
(match_operand:QI 4 "register_operand" "C"))
(match_dup 5)))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"operands[5] = CONST0_RTX (V8QImode);")
(define_insn "*vcvt<biasph2fp8_pack>v8hf_mask"
@@ -33418,7 +33418,7 @@
(const_int 6) (const_int 7)]))
(match_operand:QI 4 "register_operand" "Yk"))
(match_operand:V8QI 5 "const0_operand")))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vcvt<biasph2fp8_pack>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
[(set_attr "prefix" "evex")])
@@ -33431,12 +33431,12 @@
[(match_operand:<ssebvecmode> 1 "register_operand" "v")
(match_operand:VHF_AVX10_2_2 2 "nonimmediate_operand" "vm")]
UNSPEC_VCVTBIASPH2FP8_PACK))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vcvt<biasph2fp8_pack>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1,
%2}"
[(set_attr "prefix" "evex")])
(define_mode_iterator VHF_256_512
- [V16HF (V32HF "TARGET_AVX10_2")])
+ [V16HF (V32HF "TARGET_AVX10_2 || TARGET_AVX10V1AUX")])
(define_mode_attr ph2fp8suff
[(V32HF "") (V16HF "{y}") (V8HF "{x}")])
@@ -33458,7 +33458,7 @@
[(match_operand:V8HF 1 "nonimmediate_operand")]
UNSPEC_CONVERTPH2FP8)
(match_dup 2)))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"operands[2] = CONST0_RTX (V8QImode);")
(define_insn "*vcvt<convertph2fp8>v8hf"
@@ -33468,7 +33468,7 @@
[(match_operand:V8HF 1 "nonimmediate_operand" "vm")]
UNSPEC_CONVERTPH2FP8)
(match_operand:V8QI 2 "const0_operand")))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vcvt<convertph2fp8>{x}\t{%1, %0|%0, %1}"
[(set_attr "prefix" "evex")
(set_attr "mode" "HF")])
@@ -33488,7 +33488,7 @@
(const_int 6) (const_int 7)]))
(match_operand:QI 3 "register_operand"))
(match_dup 4)))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"operands[4] = CONST0_RTX (V8QImode);")
(define_insn "*vcvt<convertph2fp8>v8hf_mask"
@@ -33506,7 +33506,7 @@
(const_int 6) (const_int 7)]))
(match_operand:QI 3 "register_operand" "Yk"))
(match_operand:V8QI 4 "const0_operand")))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vcvt<convertph2fp8>{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
[(set_attr "prefix" "evex")])
@@ -33515,7 +33515,7 @@
(unspec:<ssebvecmode_2>
[(match_operand:VHF_256_512 1 "nonimmediate_operand" "vm")]
UNSPEC_CONVERTPH2FP8))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vcvt<convertph2fp8><ph2fp8suff>\t{%1, %0<mask_operand2>|%0<mask_operand2>,
%1}"
[(set_attr "prefix" "evex")])
@@ -33524,7 +33524,7 @@
(unspec:VHF_AVX512VL
[(match_operand:<ssebvecmode_2> 1 "nonimmediate_operand" "vm")]
UNSPEC_VCVTHF82PH))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vcvthf82ph\t{%1, %0<mask_operand2>|%0<mask_operand2>, %<iptrssebvec_2>1}"
[(set_attr "prefix" "evex")])
@@ -33546,7 +33546,7 @@
(match_operand:VI2_AVX10_2 1 "register_operand")
(match_operand:VI2_AVX10_2 2 "register_operand")
(match_operand:<sseunpackmode> 3 "register_operand")]
- "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
+ "TARGET_AVXVNNIINT16 || TARGET_AVX10_2 || TARGET_AVX10V1AUX"
{
operands[1] = lowpart_subreg (<sseunpackmode>mode,
force_reg (<MODE>mode, operands[1]),
@@ -33564,7 +33564,7 @@
(match_operand:VI2_AVX10_2 1 "register_operand")
(match_operand:VI2_AVX10_2 2 "register_operand")
(match_operand:<sseunpackmode> 3 "register_operand")]
- "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
+ "TARGET_AVXVNNIINT16 || TARGET_AVX10_2 || TARGET_AVX10V1AUX"
{
operands[1] = lowpart_subreg (<sseunpackmode>mode,
force_reg (<MODE>mode, operands[1]),
@@ -33584,7 +33584,7 @@
(match_operand:VI4_AVX 2 "register_operand" "v")
(match_operand:VI4_AVX 3 "nonimmediate_operand" "vm")]
VPDPWPROD))]
- "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
+ "TARGET_AVXVNNIINT16 || TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vpdp<vpdpwprodtype>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "prefix" "maybe_evex")])
@@ -33595,7 +33595,7 @@
(match_operand:V16SI 2 "register_operand" "v")
(match_operand:V16SI 3 "nonimmediate_operand" "vm")]
VPDPWPROD))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vpdp<vpdpwprodtype>\t{%3, %2, %0|%0, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -33609,7 +33609,7 @@
VPDPWPROD)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vpdp<vpdpwprodtype>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
[(set_attr "prefix" "evex")])
@@ -33623,7 +33623,7 @@
VPDPWPROD)
(match_dup 5)
(match_operand:<avx512fmaskmode> 4 "register_operand")))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"operands[5] = CONST0_RTX (<MODE>mode);")
(define_insn "*vpdp<vpdpwprodtype>_<mode>_maskz"
@@ -33636,7 +33636,7 @@
VPDPWPROD)
(match_operand:VI4_AVX10_2 5 "const0_operand" "C")
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
- "TARGET_AVX10_2"
+ "TARGET_AVX10_2 || TARGET_AVX10V1AUX"
"vpdp<vpdpwprodtype>\t{%3, %2, %0%{%4%}%N5|%0%{%4%}%N5, %2, %3}"
[(set_attr "prefix" "evex")])
--
2.34.1
