> From: Dipesh Sharma <[email protected]>
> Sent: Wednesday, September 23, 2026 7:05 PM
> To: [email protected]
> Cc: Jiang, Haochen <[email protected]>; [email protected]; Liu,
> Hongtao <[email protected]>; [email protected]; Dipesh
> Sharma <[email protected]>; Venkataramanan Kumar
> <[email protected]>
> Subject: [PATCH 2/4] Share builtins and md patterns from avx10.2 and
> vnniint{8,16} for avx10v1aux.
>
> This patch shares the builtins and md patterns from avx10.2 and
> vnniint{8,16} for avx10v1aux.
>
> gcc/ChangeLog:
>
> * config/i386/i386-builtin.def (BDESC): Share builtin between
> avx10.2, vnniint{8,16} and avx10v1aux.
> * config/i386/i386-builtins.cc (def_builtin): Ditto.
> * config/i386/i386-expand.cc (ix86_check_builtin_isa_match): Ditto.
> * config/i386/i386.md: Add isa target avx10v1aux.
> * config/i386/sse.md: Enable instructions for avx10v1aux.
>
> Co-authored-by: Venkataramanan Kumar
> <[email protected]>
> ---
> gcc/config/i386/i386-builtin.def | 308 +++++++++++++++----------------
> gcc/config/i386/i386-builtins.cc | 5 +-
> gcc/config/i386/i386-expand.cc | 9 +
> gcc/config/i386/i386.md | 4 +-
> gcc/config/i386/sse.md | 74 ++++----
> 5 files changed, 206 insertions(+), 194 deletions(-)
>
> diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
> index 2d250fa57b2..c9e60632497 100644
> --- a/gcc/config/i386/i386-expand.cc
> +++ b/gcc/config/i386/i386-expand.cc
> @@ -14992,6 +14992,9 @@ ix86_check_builtin_isa_match (unsigned int
> fcode,
> OPTION_MASK_ISA_AES or (OPTION_MASK_ISA_AVX512VL |
> OPTION_MASK_ISA2_VAES)
> OPTION_MASK_ISA2_AVX10_2 or OPTION_MASK_ISA2_AVXVNNIINT8
> OPTION_MASK_ISA2_AVX10_2 or OPTION_MASK_ISA2_AVXVNNIINT16
> + OPTION_MASK_ISA2_AVX10V1AUX or
> OPTION_MASK_ISA2_AVXVNNIINT8
> + OPTION_MASK_ISA2_AVX10V1AUX or
> OPTION_MASK_ISA2_AVXVNNIINT16
> + OPTION_MASK_ISA2_AVX10V1AUX or OPTION_MASK_ISA2_AVX10_2
> OPTION_MASK_ISA2_AMX_TILE or OPTION_MASK_ISA2_ACEV1
> where for each such pair it is sufficient if either of the ISAs is
> enabled, plus if it is ored with other options also those others.
> @@ -15023,6 +15026,12 @@ ix86_check_builtin_isa_match (unsigned int
> fcode,
> SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVXVNNIINT16, 0,
> OPTION_MASK_ISA2_AVX10_2);
> SHARE_BUILTIN (0, OPTION_MASK_ISA2_AMX_TILE, 0,
> OPTION_MASK_ISA2_ACEV1);
> + SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVXVNNIINT8, 0,
> + OPTION_MASK_ISA2_AVX10V1AUX);
> + SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVXVNNIINT16, 0,
> + OPTION_MASK_ISA2_AVX10V1AUX);
> + SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVX10_2, 0,
> + OPTION_MASK_ISA2_AVX10V1AUX);
> isa = tmp_isa;
> isa2 = tmp_isa2;
>
Please you also add testcases to see if this work as expected like
avxvnniint{8,16}-builtin-1.c, avx10_2-builtin-*.c.
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index e4bc746dacc..16cde4c53a0 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -715,7 +715,7 @@
> [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")])
>
> (define_mode_iterator VI4_AVX10_2
> - [(V16SI "TARGET_AVX10_2") V8SI V4SI])
> + [(V16SI "TARGET_AVX10_2 || TARGET_AVX10V1AUX") V8SI V4SI])
You should not alter this iterator since SM4 patterns are also using them.
Please use a new one.
>
> (define_mode_iterator VI48_AVX512F_AVX512VL
> [V4SI V8SI (V16SI "TARGET_AVX512F")
> @@ -33316,7 +33316,7 @@
> (match_operand:<ssePSmode> 2 "<round_nimm_predicate>"
> "<round_constraint>"))
> (float_truncate:<ssehalfvecmode>
> (match_operand:<ssePSmode> 1 "register_operand" "v"))))]
> - "TARGET_AVX10_2 && <round_mode512bit_condition>"
> + "(TARGET_AVX10_2 || TARGET_AVX10V1AUX) && <round_mode512bit_condition>"
>
> "vcvt2ps2phx\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>,
> %1, %2<round_mask_op3>}")
>
If you only touch VNNI in this patch and convert in the following up
patch, this should also be moved to the next patch and ditto for other
occurrences.
Thx,
Haochen
