AMD General Hi,
> -----Original Message----- > From: Jiang, Haochen <[email protected]> > Sent: 12 October 2026 12:48 > To: Sharma, Dipesh <[email protected]>; [email protected] > Cc: [email protected]; Liu, Hongtao <[email protected]>; > [email protected]; Kumar, Venkataramanan > <[email protected]> > Subject: RE: [PATCH 4/4] Add VNNI byte and word instructions and other test > cases. > > Caution: This message originated from an External Source. Use proper caution > when opening attachments, clicking links, or responding. > > > > From: Dipesh Sharma <[email protected]> > > Sent: Wednesday, September 23, 2026 7:05 PM > > > > This patch adds AVX10V1AUX VNNIINT8 and VNNIINT16 intrinsics, together > > with the related test coverage. > > > > The unmasked 128-bit and 256-bit forms are already provided as macros in > > avx10_2mediaintrin.h, where they shadow the earlier gnu_inline > > definitions in avxvnniint{8,16}intrin.h. > > This patch therefore only adds the masked and 512-bit wrappers as macros > in > > avx10v1auxintrin.h, > > so that they expand at the call site under -mavx10v1aux rather than > > inheriting the avx10.2 target attribute of the existing inlines. > > > > The unmasked 128/256 macros are not duplicated here. > > Open for suggestions if it is preferred to repeat those defines in > > avx10v1auxintrin.h from avx10_2mediaintrin.h and guard them with the > > respective target macro ? > > > When using macros, it will not be controlled by target macro. So > it could be seen everywhere. We utilize this feature to use the same > intrin between different CPUIDs. > > Thus, duplicating here will be redundant code but please add a > comment why unmasked 128/256 macros are not in the intrin file. > Okay. Thanks, Dipesh
