This patch adds the convert intrinsics from 10.2 to AVX10V1AUX.
gcc/ChangeLog:
* config.gcc: Add avx10v1auxintrin.h.
* config/i386/immintrin.h: Include avx10v1auxintrin.h.
* config/i386/avx10v1auxintrin.h: New file.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Added checks for avx10v1aux.
* gcc.target/i386/avx10v1aux-1a.c: New test.
Co-authored-by: Venkataramanan Kumar <[email protected]>
---
gcc/config.gcc | 2 +-
gcc/config/i386/avx10v1auxintrin.h | 859 ++++++++++++++++++
gcc/config/i386/immintrin.h | 2 +
gcc/testsuite/gcc.target/i386/avx10v1aux-1a.c | 375 ++++++++
gcc/testsuite/lib/target-supports.exp | 13 +
5 files changed, 1250 insertions(+), 1 deletion(-)
create mode 100644 gcc/config/i386/avx10v1auxintrin.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10v1aux-1a.c
diff --git a/gcc/config.gcc b/gcc/config.gcc
index e600ae272db..ec0c8ef7a01 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -480,7 +480,7 @@ i[34567]86-*-* | x86_64-*-*)
avx10_2minmaxintrin.h avx10_2copyintrin.h
amxavx512intrin.h amxfp8intrin.h movrsintrin.h
amxmovrsintrin.h avx512bmmintrin.h avx512bmmvlintrin.h
- avx10v2auxintrin.h acev1intrin.h"
+ avx10v2auxintrin.h avx10v1auxintrin.h acev1intrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/avx10v1auxintrin.h
b/gcc/config/i386/avx10v1auxintrin.h
new file mode 100644
index 00000000000..6653d32d5bc
--- /dev/null
+++ b/gcc/config/i386/avx10v1auxintrin.h
@@ -0,0 +1,859 @@
+/* Copyright (C) 2026 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+#error "Never use <avx10v1auxintrin.h> directly; include <immintrin.h>
instead."
+#endif
+
+#ifndef _AVX10V1AUXINTRIN_H_INCLUDED
+#define _AVX10V1AUXINTRIN_H_INCLUDED
+
+#if !defined(__AVX10V1AUX__)
+#pragma GCC push_options
+#pragma GCC target("avx10v1aux")
+#define __DISABLE_AVX10V1AUX__
+#endif /* __AVX10V1AUX__ */
+
+/* FP16 to FP8 converts(Single-source). */
+
+#define _mm_cvtph_bf8(A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_undefined_si128 (), \
+ (__mmask8) -1)
+
+#define _mm_mask_cvtph_bf8(W, U, A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) W, \
+ (__mmask8) U)
+
+#define _mm_maskz_cvtph_bf8(U, A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_setzero_si128 (), \
+ (__mmask8) U)
+
+#define _mm256_cvtph_bf8(A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_undefined_si128 (), \
+ (__mmask16) -1)
+
+#define _mm256_mask_cvtph_bf8(W, U, A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) W, \
+ (__mmask16) U)
+
+#define _mm256_maskz_cvtph_bf8(U, A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_setzero_si128 (), \
+ (__mmask16) U)
+
+#define _mm512_cvtph_bf8(A) \
+ (__m256i) __builtin_ia32_vcvtph2bf8512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) \
+ _mm256_undefined_si256 (),\
+ (__mmask32) -1)
+
+#define _mm512_mask_cvtph_bf8(W, U, A) \
+ (__m256i) __builtin_ia32_vcvtph2bf8512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) W, \
+ (__mmask32) U)
+
+#define _mm512_maskz_cvtph_bf8(U, A) \
+ (__m256i) __builtin_ia32_vcvtph2bf8512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) U)
+
+#define _mm_cvts_ph_bf8(A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8s128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_undefined_si128 (), \
+ (__mmask8) -1)
+
+#define _mm_mask_cvts_ph_bf8(W, U, A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8s128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) W, \
+ (__mmask8) U)
+
+#define _mm_maskz_cvts_ph_bf8(U, A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8s128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_setzero_si128 (), \
+ (__mmask8) U)
+
+#define _mm256_cvts_ph_bf8(A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8s256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_undefined_si128 (), \
+ (__mmask16) -1)
+
+#define _mm256_mask_cvts_ph_bf8(W, U, A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8s256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) W, \
+ (__mmask16) U)
+
+#define _mm256_maskz_cvts_ph_bf8(U, A) \
+ (__m128i) __builtin_ia32_vcvtph2bf8s256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_setzero_si128 (), \
+ (__mmask16) U)
+
+#define _mm512_cvts_ph_bf8(A) \
+ (__m256i) __builtin_ia32_vcvtph2bf8s512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) \
+ _mm256_undefined_si256 (),\
+ (__mmask32) -1)
+
+#define _mm512_mask_cvts_ph_bf8(W, U, A) \
+ (__m256i) __builtin_ia32_vcvtph2bf8s512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) W, \
+ (__mmask32) U)
+
+#define _mm512_maskz_cvts_ph_bf8(U, A) \
+ (__m256i) __builtin_ia32_vcvtph2bf8s512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) U)
+
+#define _mm_cvtph_hf8(A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_undefined_si128 (), \
+ (__mmask8) -1)
+
+#define _mm_mask_cvtph_hf8(W, U, A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) W, \
+ (__mmask8) U)
+
+#define _mm_maskz_cvtph_hf8(U, A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_setzero_si128 (), \
+ (__mmask8) U)
+
+#define _mm256_cvtph_hf8(A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_undefined_si128 (), \
+ (__mmask16) -1)
+
+#define _mm256_mask_cvtph_hf8(W, U, A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) W, \
+ (__mmask16) U)
+
+#define _mm256_maskz_cvtph_hf8(U, A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_setzero_si128 (), \
+ (__mmask16) U)
+
+#define _mm512_cvtph_hf8(A) \
+ (__m256i) __builtin_ia32_vcvtph2hf8512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) \
+ _mm256_undefined_si256 (),\
+ (__mmask32) -1)
+
+#define _mm512_mask_cvtph_hf8(W, U, A) \
+ (__m256i) __builtin_ia32_vcvtph2hf8512_mask ((__v32hf) A, \
+ (__v32qi)(__m256i) W, \
+ (__mmask32) U)
+
+#define _mm512_maskz_cvtph_hf8(U, A) \
+ (__m256i) __builtin_ia32_vcvtph2hf8512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) U)
+
+#define _mm_cvts_ph_hf8(A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8s128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_undefined_si128 (), \
+ (__mmask8) -1)
+
+#define _mm_mask_cvts_ph_hf8(W, U, A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8s128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) W, \
+ (__mmask8) U)
+
+#define _mm_maskz_cvts_ph_hf8(U, A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8s128_mask ((__v8hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_setzero_si128 (), \
+ (__mmask8) U)
+
+#define _mm256_cvts_ph_hf8(A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8s256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_undefined_si128 (), \
+ (__mmask16) -1)
+
+#define _mm256_mask_cvts_ph_hf8(W, U, A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8s256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) W, \
+ (__mmask16) U)
+
+#define _mm256_maskz_cvts_ph_hf8(U, A) \
+ (__m128i) __builtin_ia32_vcvtph2hf8s256_mask ((__v16hf) A, \
+ (__v16qi)(__m128i) \
+ _mm_setzero_si128 (), \
+ (__mmask16) U)
+
+#define _mm512_cvts_ph_hf8(A) \
+ (__m256i) __builtin_ia32_vcvtph2hf8s512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) \
+ _mm256_undefined_si256 (),\
+ (__mmask32) -1)
+
+#define _mm512_mask_cvts_ph_hf8(W, U, A) \
+ (__m256i) __builtin_ia32_vcvtph2hf8s512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) W, \
+ (__mmask32) U)
+
+#define _mm512_maskz_cvts_ph_hf8(U, A) \
+ (__m256i) __builtin_ia32_vcvtph2hf8s512_mask ((__v32hf) A, \
+ (__v32qi) (__m256i) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) U)
+
+/* FP16 to FP8 converts(Two-source). */
+
+#define _mm_cvt2ph_bf8(A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2bf8128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (), \
+ (__mmask16) -1)
+
+#define _mm_mask_cvt2ph_bf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2bf8128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) W, \
+ (__mmask16) U)
+
+#define _mm_maskz_cvt2ph_bf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2bf8128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (), \
+ (__mmask16) U)
+
+#define _mm256_cvt2ph_bf8(A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2bf8256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) -1)
+
+#define _mm256_mask_cvt2ph_bf8(W, U, A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2bf8256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) W, \
+ (__mmask32) U)
+
+#define _mm256_maskz_cvt2ph_bf8(U, A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2bf8256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) U)
+
+#define _mm512_cvt2ph_bf8(A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2bf8512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) \
+ _mm512_setzero_si512 (), \
+ (__mmask64) -1)
+
+#define _mm512_mask_cvt2ph_bf8(W, U, A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2bf8512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) W, \
+ (__mmask64) U)
+
+#define _mm512_maskz_cvt2ph_bf8(U, A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2bf8512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) \
+ _mm512_setzero_si512 (), \
+ (__mmask64) U)
+
+#define _mm_cvts_2ph_bf8(A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2bf8s128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (), \
+ (__mmask16) -1)
+
+#define _mm_mask_cvts_2ph_bf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2bf8s128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) W, \
+ (__mmask16) U)
+
+#define _mm_maskz_cvts_2ph_bf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2bf8s128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (), \
+ (__mmask16) U)
+
+#define _mm256_cvts_2ph_bf8(A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2bf8s256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) -1)
+
+#define _mm256_mask_cvts_2ph_bf8(W, U, A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2bf8s256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) W, \
+ (__mmask32) U)
+
+#define _mm256_maskz_cvts_2ph_bf8(U, A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2bf8s256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) U)
+
+#define _mm512_cvts_2ph_bf8(A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2bf8s512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) \
+ _mm512_setzero_si512 (), \
+ (__mmask64) -1)
+
+#define _mm512_mask_cvts_2ph_bf8(W, U, A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2bf8s512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) W, \
+ (__mmask64) U)
+
+#define _mm512_maskz_cvts_2ph_bf8(U, A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2bf8s512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) \
+ _mm512_setzero_si512 (), \
+ (__mmask64) U)
+
+#define _mm_cvt2ph_hf8(A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2hf8128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (), \
+ (__mmask16) -1)
+
+#define _mm_mask_cvt2ph_hf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2hf8128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) W, \
+ (__mmask16) U)
+
+#define _mm_maskz_cvt2ph_hf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2hf8128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (), \
+ (__mmask16) U)
+
+#define _mm256_cvt2ph_hf8(A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2hf8256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) -1)
+
+#define _mm256_mask_cvt2ph_hf8(W, U, A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2hf8256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) W, \
+ (__mmask32) U)
+
+#define _mm256_maskz_cvt2ph_hf8(U, A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2hf8256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) U)
+
+#define _mm512_cvt2ph_hf8(A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2hf8512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) \
+ _mm512_setzero_si512 (), \
+ (__mmask64) -1)
+
+#define _mm512_mask_cvt2ph_hf8(W, U, A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2hf8512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) W, \
+ (__mmask64) U)
+
+#define _mm512_maskz_cvt2ph_hf8(U, A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2hf8512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) \
+ _mm512_setzero_si512 (), \
+ (__mmask64) U)
+
+#define _mm_cvts_2ph_hf8(A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2hf8s128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (), \
+ (__mmask16) -1)
+
+#define _mm_mask_cvts_2ph_hf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2hf8s128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) W, \
+ (__mmask16) U)
+
+#define _mm_maskz_cvts_2ph_hf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvt2ph2hf8s128_mask ((__v8hf) A, \
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (), \
+ (__mmask16) U)
+
+#define _mm256_cvts_2ph_hf8(A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2hf8s256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) -1)
+
+#define _mm256_mask_cvts_2ph_hf8(W, U, A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2hf8s256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) W, \
+ (__mmask32) U)
+
+#define _mm256_maskz_cvts_2ph_hf8(U, A, B) \
+ (__m256i) __builtin_ia32_vcvt2ph2hf8s256_mask ((__v16hf) A, \
+ (__v16hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (), \
+ (__mmask32) U)
+
+#define _mm512_cvts_2ph_hf8(A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2hf8s512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) \
+ _mm512_setzero_si512 (), \
+ (__mmask64) -1)
+
+#define _mm512_mask_cvts_2ph_hf8(W, U, A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2hf8s512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) W, \
+ (__mmask64) U)
+
+#define _mm512_maskz_cvts_2ph_hf8(U, A, B) \
+ (__m512i) __builtin_ia32_vcvt2ph2hf8s512_mask ((__v32hf) A, \
+ (__v32hf) B, \
+ (__v64qi) \
+ _mm512_setzero_si512 (), \
+ (__mmask64) U)
+
+/* FP16 to FP8 Converts (Biased) */
+
+#define _mm_cvtbiasph_bf8(A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8128 ((__v16qi) A, \
+ (__v8hf) B)
+
+#define _mm_mask_cvtbiasph_bf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8128_mask ((__v16qi) A,
\
+ (__v8hf) B, \
+ (__v16qi) W, \
+ (__mmask8) U)
+
+#define _mm_maskz_cvtbiasph_bf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8128_mask ((__v16qi) A,
\
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (),\
+ (__mmask8) U)
+
+#define _mm256_cvtbiasph_bf8(A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8256_mask ((__v32qi) A,
\
+ (__v16hf) B, \
+ (__v16qi) \
+ _mm_undefined_si128 (),\
+ (__mmask16) -1)
+
+#define _mm256_mask_cvtbiasph_bf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8256_mask ((__v32qi) A,
\
+ (__v16hf) B, \
+ (__v16qi) W, \
+ (__mmask16) U)
+
+#define _mm256_maskz_cvtbiasph_bf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8256_mask ((__v32qi) A,
\
+ (__v16hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (),\
+ (__mmask16) U)
+
+#define _mm512_cvtbiasph_bf8(A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2bf8512_mask ((__v64qi) A,
\
+ (__v32hf) B, \
+ (__v32qi) \
+ _mm256_undefined_si256 (),\
+ (__mmask32) -1)
+
+#define _mm512_mask_cvtbiasph_bf8(W, U, A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2bf8512_mask ((__v64qi) A,
\
+ (__v32hf) B, \
+ (__v32qi) W, \
+ (__mmask32) U)
+
+#define _mm512_maskz_cvtbiasph_bf8(U, A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2bf8512_mask ((__v64qi) A,
\
+ (__v32hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (),\
+ (__mmask32) U)
+
+#define _mm_cvts_biasph_bf8(A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8s128 ((__v16qi) A, \
+ (__v8hf) B)
+
+#define _mm_mask_cvts_biasph_bf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8s128_mask ((__v16qi) A, \
+ (__v8hf) B, \
+ (__v16qi) W, \
+ (__mmask8) U)
+
+#define _mm_maskz_cvts_biasph_bf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8s128_mask ((__v16qi) A, \
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (),\
+ (__mmask8) U)
+
+#define _mm256_cvts_biasph_bf8(A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8s256_mask ((__v32qi) A, \
+ (__v16hf) B, \
+ (__v16qi)(__m128i) \
+ _mm_undefined_si128 (),\
+ (__mmask16) -1)
+
+#define _mm256_mask_cvts_biasph_bf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8s256_mask ((__v32qi) A, \
+ (__v16hf) B, \
+ (__v16qi) W, \
+ (__mmask16) U)
+
+#define _mm256_maskz_cvts_biasph_bf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2bf8s256_mask ((__v32qi) A, \
+ (__v16hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (),\
+ (__mmask16) U)
+
+#define _mm512_cvts_biasph_bf8(A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2bf8s512_mask ((__v64qi) A, \
+ (__v32hf) B, \
+ (__v32qi) \
+ _mm256_undefined_si256 (),\
+ (__mmask32) -1)
+
+#define _mm512_mask_cvts_biasph_bf8(W, U, A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2bf8s512_mask ((__v64qi) A, \
+ (__v32hf) B, \
+ (__v32qi) W, \
+ (__mmask32) U)
+
+#define _mm512_maskz_cvts_biasph_bf8(U, A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2bf8s512_mask ((__v64qi) A, \
+ (__v32hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (),\
+ (__mmask32) U)
+
+#define _mm_cvtbiasph_hf8(A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8128 ((__v16qi) A, \
+ (__v8hf) B)
+
+#define _mm_mask_cvtbiasph_hf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8128_mask ((__v16qi) A,
\
+ (__v8hf) B, \
+ (__v16qi) W, \
+ (__mmask8) U)
+
+#define _mm_maskz_cvtbiasph_hf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8128_mask ((__v16qi) A,
\
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (),\
+ (__mmask8) U)
+
+#define _mm256_cvtbiasph_hf8(A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8256_mask ((__v32qi) A,
\
+ (__v16hf) B, \
+ (__v16qi) \
+ _mm_undefined_si128 (),\
+ (__mmask16) -1)
+
+#define _mm256_mask_cvtbiasph_hf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8256_mask ((__v32qi) A,
\
+ (__v16hf) B, \
+ (__v16qi) W, \
+ (__mmask16) U)
+
+#define _mm256_maskz_cvtbiasph_hf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8256_mask ((__v32qi) A,
\
+ (__v16hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (),\
+ (__mmask16) U)
+
+#define _mm512_cvtbiasph_hf8(A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2hf8512_mask ((__v64qi) A,
\
+ (__v32hf) B, \
+ (__v32qi) \
+ _mm256_undefined_si256 (),\
+ (__mmask32) -1)
+
+#define _mm512_mask_cvtbiasph_hf8(W, U, A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2hf8512_mask ((__v64qi) A,
\
+ (__v32hf) B, \
+ (__v32qi) W, \
+ (__mmask32) U)
+
+#define _mm512_maskz_cvtbiasph_hf8(U, A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2hf8512_mask ((__v64qi) A,
\
+ (__v32hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (),\
+ (__mmask32) U)
+
+#define _mm_cvts_biasph_hf8(A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8s128 ((__v16qi) A, \
+ (__v8hf) B)
+
+#define _mm_mask_cvts_biasph_hf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8s128_mask ((__v16qi) A, \
+ (__v8hf) B, \
+ (__v16qi) W, \
+ (__mmask8) U)
+
+#define _mm_maskz_cvts_biasph_hf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8s128_mask ((__v16qi) A, \
+ (__v8hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (),\
+ (__mmask8) U)
+
+#define _mm256_cvts_biasph_hf8(A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8s256_mask ((__v32qi) A, \
+ (__v16hf) B, \
+ (__v16qi) \
+ _mm_undefined_si128 (),\
+ (__mmask16) -1)
+
+#define _mm256_mask_cvts_biasph_hf8(W, U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8s256_mask ((__v32qi) A, \
+ (__v16hf) B, \
+ (__v16qi) W, \
+ (__mmask16) U)
+
+#define _mm256_maskz_cvts_biasph_hf8(U, A, B) \
+ (__m128i) __builtin_ia32_vcvtbiasph2hf8s256_mask ((__v32qi) A, \
+ (__v16hf) B, \
+ (__v16qi) \
+ _mm_setzero_si128 (),\
+ (__mmask16) U)
+
+#define _mm512_cvts_biasph_hf8(A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2hf8s512_mask ((__v64qi) A, \
+ (__v32hf) B, \
+ (__v32qi) \
+ _mm256_undefined_si256 (),\
+ (__mmask32) -1)
+
+#define _mm512_mask_cvts_biasph_hf8(W, U, A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2hf8s512_mask ((__v64qi) A, \
+ (__v32hf) B, \
+ (__v32qi) W, \
+ (__mmask32) U)
+
+#define _mm512_maskz_cvts_biasph_hf8(U, A, B) \
+ (__m256i) __builtin_ia32_vcvtbiasph2hf8s512_mask ((__v64qi) A, \
+ (__v32hf) B, \
+ (__v32qi) \
+ _mm256_setzero_si256 (),\
+ (__mmask32) U)
+
+/* FP8 to FP16 Converts */
+
+#define _mm_cvthf8_ph(A) \
+ (__m128h) __builtin_ia32_vcvthf82ph128_mask ((__v16qi) A, \
+ (__v8hf)(__m128h) \
+ _mm_undefined_ph (), \
+ (__mmask8) -1)
+
+#define _mm_mask_cvthf8_ph(W, U, A) \
+ (__m128h) __builtin_ia32_vcvthf82ph128_mask ((__v16qi) A, \
+ (__v8hf)(__m128h) W, \
+ (__mmask8) U)
+
+#define _mm_maskz_cvthf8_ph(U, A) \
+ (__m128h) __builtin_ia32_vcvthf82ph128_mask ((__v16qi) A, \
+ (__v8hf)(__m128h) \
+ _mm_setzero_ph (), \
+ (__mmask8) U)
+
+#define _mm256_cvthf8_ph(A) \
+ (__m256h) __builtin_ia32_vcvthf82ph256_mask ((__v16qi) A, \
+ (__v16hf)(__m256h) \
+ _mm256_undefined_ph (),\
+ (__mmask16) -1)
+
+#define _mm256_mask_cvthf8_ph(W, U, A) \
+ (__m256h) __builtin_ia32_vcvthf82ph256_mask ((__v16qi) A, \
+ (__v16hf)(__m256h) W, \
+ (__mmask16) U)
+
+#define _mm256_maskz_cvthf8_ph(U, A) \
+ (__m256h) __builtin_ia32_vcvthf82ph256_mask ((__v16qi) A, \
+ (__v16hf)(__m256h) \
+ _mm256_setzero_ph (), \
+ (__mmask16) U)
+
+#define _mm512_cvthf8_ph(A) \
+ (__m512h) __builtin_ia32_vcvthf82ph512_mask ((__v32qi) A, \
+ (__v32hf)(__m512h) \
+ _mm512_undefined_ph (),\
+ (__mmask32) -1)
+
+#define _mm512_mask_cvthf8_ph(W, U, A) \
+ (__m512h) __builtin_ia32_vcvthf82ph512_mask ((__v32qi) A, \
+ (__v32hf)(__m512h) W, \
+ (__mmask32) U)
+
+#define _mm512_maskz_cvthf8_ph(U, A) \
+ (__m512h) __builtin_ia32_vcvthf82ph512_mask ((__v32qi) A, \
+ (__v32hf)(__m512h) \
+ _mm512_setzero_ph (), \
+ (__mmask32) U)
+
+/* FP32-Pair to FP16 Converts */
+
+#define _mm_cvtx2ps_ph(A, B) \
+ (__m128h) __builtin_ia32_vcvt2ps2phx128_mask ((__v4sf) A, \
+ (__v4sf) B, \
+ (__v8hf) \
+ _mm_setzero_ph (), \
+ (__mmask8) -1)
+
+#define _mm_mask_cvtx2ps_ph(W, U, A, B) \
+ (__m128h) __builtin_ia32_vcvt2ps2phx128_mask ((__v4sf) A, \
+ (__v4sf) B, \
+ (__v8hf) W, \
+ (__mmask8) U)
+
+#define _mm_maskz_cvtx2ps_ph(U, A, B) \
+ (__m128h) __builtin_ia32_vcvt2ps2phx128_mask ((__v4sf) A, \
+ (__v4sf) B, \
+ (__v8hf) \
+ _mm_setzero_ph (), \
+ (__mmask8) U)
+
+#define _mm256_cvtx2ps_ph(A, B) \
+ (__m256h) __builtin_ia32_vcvt2ps2phx256_mask ((__v8sf) A, \
+ (__v8sf) B, \
+ (__v16hf) \
+ _mm256_setzero_ph (), \
+ (__mmask16) -1)
+
+#define _mm256_mask_cvtx2ps_ph(W, U, A, B) \
+ (__m256h) __builtin_ia32_vcvt2ps2phx256_mask ((__v8sf) A, \
+ (__v8sf) B, \
+ (__v16hf) W, \
+ (__mmask16) U)
+
+#define _mm256_maskz_cvtx2ps_ph(U, A, B) \
+ (__m256h) __builtin_ia32_vcvt2ps2phx256_mask ((__v8sf) A, \
+ (__v8sf) B, \
+ (__v16hf) \
+ _mm256_setzero_ph (), \
+ (__mmask16) U)
+
+#define _mm512_cvtx2ps_ph(A, B)
\
+ (__m512h) __builtin_ia32_vcvt2ps2phx512_mask_round ((__v16sf) A,
\
+ (__v16sf) B,
\
+ (__v32hf)
\
+ _mm512_setzero_ph (),
\
+ (__mmask32) -1,
\
+
_MM_FROUND_CUR_DIRECTION)
+
+#define _mm512_mask_cvtx2ps_ph(W, U, A, B)
\
+ (__m512h) __builtin_ia32_vcvt2ps2phx512_mask_round ((__v16sf) A,
\
+ (__v16sf) B,
\
+ (__v32hf) W,
\
+ (__mmask32) U,
\
+
_MM_FROUND_CUR_DIRECTION)
+
+#define _mm512_maskz_cvtx2ps_ph(U, A, B)
\
+ (__m512h) __builtin_ia32_vcvt2ps2phx512_mask_round ((__v16sf) A,
\
+ (__v16sf) B,
\
+ (__v32hf)
\
+ _mm512_setzero_ph (),
\
+ (__mmask32) U,
\
+
_MM_FROUND_CUR_DIRECTION)
+
+#define _mm512_cvtx_round2ps_ph(A, B, R)
\
+ ((__m512h) __builtin_ia32_vcvt2ps2phx512_mask_round ((__v16sf) (A),
\
+ (__v16sf) (B),
\
+ (__v32hf)
\
+ (_mm512_setzero_ph ()),
\
+ (__mmask32) (-1),
\
+ (R)))
+#define _mm512_mask_cvtx_round2ps_ph(W, U, A, B, R)
\
+ (__m512h) __builtin_ia32_vcvt2ps2phx512_mask_round ((__v16sf) A,
\
+ (__v16sf) B,
\
+ (__v32hf) W,
\
+ (__mmask32) U,
\
+ R)
+#define _mm512_maskz_cvtx_round2ps_ph(U, A, B, R) \
+ (__m512h) __builtin_ia32_vcvt2ps2phx512_mask_round ((__v16sf) A,
\
+ (__v16sf) B,
\
+ (__v32hf)
\
+ _mm512_setzero_ph (),
\
+ (__mmask32) U,
\
+ R)
+
+#ifdef __DISABLE_AVX10V1AUX__
+#undef __DISABLE_AVX10V1AUX__
+#pragma GCC pop_options
+#endif /* __DISABLE_AVX10V1AUX__ */
+
+#endif /* __AVX10V1AUXINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 63db4fddca6..74063ee4053 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -148,6 +148,8 @@
#include <avx10v2auxintrin.h>
+#include <avx10v1auxintrin.h>
+
#include <avx10_2bf16intrin.h>
#include <avx10_2satcvtintrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx10v1aux-1a.c
b/gcc/testsuite/gcc.target/i386/avx10v1aux-1a.c
new file mode 100644
index 00000000000..369ec969dde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10v1aux-1a.c
@@ -0,0 +1,375 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10v1aux -O2 -fno-fuse-ops-with-volatile-access" } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ps2phx\[
\\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82ph\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82ph\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvthf82ph\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvthf82ph\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82ph\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvthf82ph\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvthf82ph\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82ph\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvthf82ph\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8x\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8x\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2bf8x\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8y\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8y\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2bf8y\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2bf8\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8sx\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8sx\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2bf8sx\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8sy\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8sy\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2bf8sy\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8s\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2bf8s\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2bf8s\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8x\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8x\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2hf8x\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8y\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8y\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2hf8y\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2hf8\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8sx\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8sx\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2hf8sx\[
\\t\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8sy\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8sy\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2hf8sy\[
\\t\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8s\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2hf8s\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } }
*/
+/* { dg-final { scan-assembler-times "vcvtph2hf8s\[
\\t\]*%zmm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1
} } */
+
+#include <immintrin.h>
+
+volatile __m128 a1,b1;
+volatile __m256 a2,b2;
+volatile __m512 a3,b3;
+volatile __m128h y,x128h,z;
+volatile __m256h y2,x256h,z2;
+volatile __m512h y3,x512h,z4;
+volatile __m128i x128i,z3;
+volatile __m256i x256i,z1;
+volatile __m512i x512i;
+volatile __mmask8 m8;
+volatile __mmask16 m16;
+volatile __mmask32 m32;
+volatile __mmask64 m64;
+
+void extern
+avx10v1aux_test (void)
+{
+ y = _mm_cvtx2ps_ph (a1, b1);
+ y = _mm_mask_cvtx2ps_ph (y, m8, a1, b1);
+ y = _mm_maskz_cvtx2ps_ph (m8, a1, b1);
+
+ y2 = _mm256_cvtx2ps_ph (a2, b2);
+ y2 = _mm256_mask_cvtx2ps_ph (y2, m16, a2, b2);
+ y2 = _mm256_maskz_cvtx2ps_ph (m16, a2, b2);
+
+ y3 = _mm512_cvtx2ps_ph (a3, b3);
+ y3 = _mm512_mask_cvtx2ps_ph (y3, m32, a3, b3);
+ y3 = _mm512_maskz_cvtx2ps_ph (m32, a3, b3);
+
+ y3 = _mm512_cvtx_round2ps_ph (a3, b3, 8);
+ y3 = _mm512_mask_cvtx_round2ps_ph (y3, m32, a3, b3, 8);
+ y3 = _mm512_maskz_cvtx_round2ps_ph (m32, a3, b3, 8);
+}
+
+void extern
+avx10v1aux_vcvtbiasph2bf8_test (void)
+{
+ x128i = _mm_cvtbiasph_bf8 (x128i, x128h);
+ x128i = _mm_mask_cvtbiasph_bf8 (x128i, m8, x128i, x128h);
+ x128i = _mm_maskz_cvtbiasph_bf8 (m8, x128i, x128h);
+
+ x128i = _mm256_cvtbiasph_bf8 (x256i, x256h);
+ x128i = _mm256_mask_cvtbiasph_bf8 (x128i, m16, x256i, x256h);
+ x128i = _mm256_maskz_cvtbiasph_bf8 (m16, x256i, x256h);
+
+ x256i = _mm512_cvtbiasph_bf8 (x512i, x512h);
+ x256i = _mm512_mask_cvtbiasph_bf8 (x256i, m32, x512i, x512h);
+ x256i = _mm512_maskz_cvtbiasph_bf8 (m32, x512i, x512h);
+}
+
+void extern
+avx10v1aux_vcvtbiasph2bf8s_test (void)
+{
+ x128i = _mm_cvts_biasph_bf8 (x128i, x128h);
+ x128i = _mm_mask_cvts_biasph_bf8 (x128i, m8, x128i, x128h);
+ x128i = _mm_maskz_cvts_biasph_bf8 (m8, x128i, x128h);
+
+ x128i = _mm256_cvts_biasph_bf8 (x256i, x256h);
+ x128i = _mm256_mask_cvts_biasph_bf8 (x128i, m16, x256i, x256h);
+ x128i = _mm256_maskz_cvts_biasph_bf8 (m16, x256i, x256h);
+
+ x256i = _mm512_cvts_biasph_bf8 (x512i, x512h);
+ x256i = _mm512_mask_cvts_biasph_bf8 (x256i, m32, x512i, x512h);
+ x256i = _mm512_maskz_cvts_biasph_bf8 (m32, x512i, x512h);
+}
+
+void extern
+avx10v1aux_vcvtbiasph2hf8_test (void)
+{
+ x128i = _mm_cvtbiasph_hf8 (x128i, x128h);
+ x128i = _mm_mask_cvtbiasph_hf8 (x128i, m8, x128i, x128h);
+ x128i = _mm_maskz_cvtbiasph_hf8 (m8, x128i, x128h);
+
+ x128i = _mm256_cvtbiasph_hf8 (x256i, x256h);
+ x128i = _mm256_mask_cvtbiasph_hf8 (x128i, m16, x256i, x256h);
+ x128i = _mm256_maskz_cvtbiasph_hf8 (m16, x256i, x256h);
+
+ x256i = _mm512_cvtbiasph_hf8 (x512i, x512h);
+ x256i = _mm512_mask_cvtbiasph_hf8 (x256i, m32, x512i, x512h);
+ x256i = _mm512_maskz_cvtbiasph_hf8 (m32, x512i, x512h);
+}
+
+void extern
+avx10v1aux_vcvtbiasph2hf8s_test (void)
+{
+ x128i = _mm_cvts_biasph_hf8 (x128i, x128h);
+ x128i = _mm_mask_cvts_biasph_hf8 (x128i, m8, x128i, x128h);
+ x128i = _mm_maskz_cvts_biasph_hf8 (m8, x128i, x128h);
+
+ x128i = _mm256_cvts_biasph_hf8 (x256i, x256h);
+ x128i = _mm256_mask_cvts_biasph_hf8 (x128i, m16, x256i, x256h);
+ x128i = _mm256_maskz_cvts_biasph_hf8 (m16, x256i, x256h);
+
+ x256i = _mm512_cvts_biasph_hf8 (x512i, x512h);
+ x256i = _mm512_mask_cvts_biasph_hf8 (x256i, m32, x512i, x512h);
+ x256i = _mm512_maskz_cvts_biasph_hf8 (m32, x512i, x512h);
+}
+
+void extern
+avx10v1aux_vcvt2ph2bf8_test (void)
+{
+ x128i = _mm_cvt2ph_bf8 (x128h, x128h);
+ x128i = _mm_mask_cvt2ph_bf8 (x128i, m16, x128h, x128h);
+ x128i = _mm_maskz_cvt2ph_bf8 (m16, x128h, x128h);
+
+ x256i = _mm256_cvt2ph_bf8 (x256h, x256h);
+ x256i = _mm256_mask_cvt2ph_bf8 (x256i, m32, x256h, x256h);
+ x256i = _mm256_maskz_cvt2ph_bf8 (m32, x256h, x256h);
+
+ x512i = _mm512_cvt2ph_bf8 (x512h, x512h);
+ x512i = _mm512_mask_cvt2ph_bf8 (x512i, m64, x512h, x512h);
+ x512i = _mm512_maskz_cvt2ph_bf8 (m64, x512h, x512h);
+}
+
+void extern
+avx10v1aux_vcvt2ph2bf8s_test (void)
+{
+ x128i = _mm_cvts_2ph_bf8 (x128h, x128h);
+ x128i = _mm_mask_cvts_2ph_bf8 (x128i, m16, x128h, x128h);
+ x128i = _mm_maskz_cvts_2ph_bf8 (m16, x128h, x128h);
+
+ x256i = _mm256_cvts_2ph_bf8 (x256h, x256h);
+ x256i = _mm256_mask_cvts_2ph_bf8 (x256i, m32, x256h, x256h);
+ x256i = _mm256_maskz_cvts_2ph_bf8 (m32, x256h, x256h);
+
+ x512i = _mm512_cvts_2ph_bf8 (x512h, x512h);
+ x512i = _mm512_mask_cvts_2ph_bf8 (x512i, m64, x512h, x512h);
+ x512i = _mm512_maskz_cvts_2ph_bf8 (m64, x512h, x512h);
+}
+
+void extern
+avx10v1aux_vcvt2ph2hf8_test (void)
+{
+ x128i = _mm_cvt2ph_hf8 (x128h, x128h);
+ x128i = _mm_mask_cvt2ph_hf8 (x128i, m16, x128h, x128h);
+ x128i = _mm_maskz_cvt2ph_hf8 (m16, x128h, x128h);
+
+ x256i = _mm256_cvt2ph_hf8 (x256h, x256h);
+ x256i = _mm256_mask_cvt2ph_hf8 (x256i, m32, x256h, x256h);
+ x256i = _mm256_maskz_cvt2ph_hf8 (m32, x256h, x256h);
+
+ x512i = _mm512_cvt2ph_hf8 (x512h, x512h);
+ x512i = _mm512_mask_cvt2ph_hf8 (x512i, m64, x512h, x512h);
+ x512i = _mm512_maskz_cvt2ph_hf8 (m64, x512h, x512h);
+}
+
+void extern
+avx10v1aux_vcvt2ph2hf8s_test (void)
+{
+ x128i = _mm_cvts_2ph_hf8 (x128h, x128h);
+ x128i = _mm_mask_cvts_2ph_hf8 (x128i, m16, x128h, x128h);
+ x128i = _mm_maskz_cvts_2ph_hf8 (m16, x128h, x128h);
+
+ x256i = _mm256_cvts_2ph_hf8 (x256h, x256h);
+ x256i = _mm256_mask_cvts_2ph_hf8 (x256i, m32, x256h, x256h);
+ x256i = _mm256_maskz_cvts_2ph_hf8 (m32, x256h, x256h);
+
+ x512i = _mm512_cvts_2ph_hf8 (x512h, x512h);
+ x512i = _mm512_mask_cvts_2ph_hf8 (x512i, m64, x512h, x512h);
+ x512i = _mm512_maskz_cvts_2ph_hf8 (m64, x512h, x512h);
+}
+
+void extern
+avx10v1aux_vcvthf82ph_test (void)
+{
+ x128h = _mm_cvthf8_ph (x128i);
+ x128h = _mm_mask_cvthf8_ph (x128h, m8, x128i);
+ x128h = _mm_maskz_cvthf8_ph (m8, x128i);
+
+ x256h = _mm256_cvthf8_ph (x128i);
+ x256h = _mm256_mask_cvthf8_ph (x256h, m16, x128i);
+ x256h = _mm256_maskz_cvthf8_ph (m16, x128i);
+
+ x512h = _mm512_cvthf8_ph (x256i);
+ x512h = _mm512_mask_cvthf8_ph (x512h, m32, x256i);
+ x512h = _mm512_maskz_cvthf8_ph (m32, x256i);
+}
+
+void extern
+avx10v1aux_vcvtph2bf8_test (void)
+{
+ x128i = _mm_cvtph_bf8 (x128h);
+ x128i = _mm_mask_cvtph_bf8 (x128i, m8, x128h);
+ x128i = _mm_maskz_cvtph_bf8 (m8, x128h);
+
+ x128i = _mm256_cvtph_bf8 (x256h);
+ x128i = _mm256_mask_cvtph_bf8 (x128i, m16, x256h);
+ x128i = _mm256_maskz_cvtph_bf8 (m16, x256h);
+
+ x256i = _mm512_cvtph_bf8 (x512h);
+ x256i = _mm512_mask_cvtph_bf8 (x256i, m32, x512h);
+ x256i = _mm512_maskz_cvtph_bf8 (m32, x512h);
+}
+
+void extern
+avx10v1aux_vcvtph2bf8s_test (void)
+{
+ x128i = _mm_cvts_ph_bf8 (x128h);
+ x128i = _mm_mask_cvts_ph_bf8 (x128i, m8, x128h);
+ x128i = _mm_maskz_cvts_ph_bf8 (m8, x128h);
+
+ x128i = _mm256_cvts_ph_bf8 (x256h);
+ x128i = _mm256_mask_cvts_ph_bf8 (x128i, m16, x256h);
+ x128i = _mm256_maskz_cvts_ph_bf8 (m16, x256h);
+
+ x256i = _mm512_cvts_ph_bf8 (x512h);
+ x256i = _mm512_mask_cvts_ph_bf8 (x256i, m32, x512h);
+ x256i = _mm512_maskz_cvts_ph_bf8 (m32, x512h);
+}
+
+void extern
+avx10v1aux_vcvtph2hf8_test (void)
+{
+ x128i = _mm_cvtph_hf8 (x128h);
+ x128i = _mm_mask_cvtph_hf8 (x128i, m8, x128h);
+ x128i = _mm_maskz_cvtph_hf8 (m8, x128h);
+
+ x128i = _mm256_cvtph_hf8 (x256h);
+ x128i = _mm256_mask_cvtph_hf8 (x128i, m16, x256h);
+ x128i = _mm256_maskz_cvtph_hf8 (m16, x256h);
+
+ x256i = _mm512_cvtph_hf8 (x512h);
+ x256i = _mm512_mask_cvtph_hf8 (x256i, m32, x512h);
+ x256i = _mm512_maskz_cvtph_hf8 (m32, x512h);
+}
+
+void extern
+avx10v1aux_vcvtph2hf8s_test (void)
+{
+ x128i = _mm_cvts_ph_hf8 (x128h);
+ x128i = _mm_mask_cvts_ph_hf8 (x128i, m8, x128h);
+ x128i = _mm_maskz_cvts_ph_hf8 (m8, x128h);
+
+ x128i = _mm256_cvts_ph_hf8 (x256h);
+ x128i = _mm256_mask_cvts_ph_hf8 (x128i, m16, x256h);
+ x128i = _mm256_maskz_cvts_ph_hf8 (m16, x256h);
+
+ x256i = _mm512_cvts_ph_hf8 (x512h);
+ x256i = _mm512_mask_cvts_ph_hf8 (x256i, m32, x512h);
+ x256i = _mm512_maskz_cvts_ph_hf8 (m32, x512h);
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ab726f729ab..9569f5cb34a 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11744,6 +11744,19 @@ proc check_effective_target_avx10v2aux { } {
} "-mavx10v2aux" ]
}
+# Return 1 if avx10v1aux instructions can be compiled.
+proc check_effective_target_avx10v1aux { } {
+ return [check_no_compiler_messages avx10v1aux object {
+ void
+ foo ()
+ {
+ __asm__ volatile ("vpdpbssds\t{%%zmm2, %%zmm1 %%zmm0|%%zmm0, %%zmm1
%%zmm2}");
+ __asm__ volatile ("vpdpwsud\t{%%zmm2, %%zmm1 %%zmm0|%%zmm0, %%zmm1
%%zmm2}");
+ __asm__ volatile ("vcvt2ph2bf8\t{%%zmm2, %%zmm1 %%zmm1|%%zmm1, %%zmm1
%%zmm2}");
+ }
+ } "-mavx10v1aux" ]
+}
+
# Return 1 if amx-avx512 instructions can be compiled.
proc check_effective_target_amx_avx512 { } {
return [check_no_compiler_messages amx_avx512 object {
--
2.34.1
