> From: Dipesh Sharma <[email protected]> > Sent: Wednesday, September 23, 2026 7:05 PM > > This patch adds AVX10V1AUX VNNIINT8 and VNNIINT16 intrinsics, together > with the related test coverage. > > The unmasked 128-bit and 256-bit forms are already provided as macros in > avx10_2mediaintrin.h, where they shadow the earlier gnu_inline > definitions in avxvnniint{8,16}intrin.h. > This patch therefore only adds the masked and 512-bit wrappers as macros in > avx10v1auxintrin.h, > so that they expand at the call site under -mavx10v1aux rather than > inheriting the avx10.2 target attribute of the existing inlines. > > The unmasked 128/256 macros are not duplicated here. > Open for suggestions if it is preferred to repeat those defines in > avx10v1auxintrin.h from avx10_2mediaintrin.h and guard them with the > respective target macro ?
When using macros, it will not be controlled by target macro. So it could be seen everywhere. We utilize this feature to use the same intrin between different CPUIDs. Thus, duplicating here will be redundant code but please add a comment why unmasked 128/256 macros are not in the intrin file. Thx, Haochen > > gcc/ChangeLog: > > * config/i386/avx10v1auxintrin.h: Added vnni byte and word > intrinsics for avx10v1aux. > > gcc/testsuite/ChangeLog: > > * g++.dg/other/i386-2.C: Added tests for avx10v1aux. > * g++.dg/other/i386-3.C: Ditto. > * gcc.target/i386/avx-1.c: Ditto. > * gcc.target/i386/funcspec-56.inc: Ditto. > * gcc.target/i386/sse-12.c: Ditto. > * gcc.target/i386/sse-13.c: Ditto. > * gcc.target/i386/sse-14.c: Ditto. > * gcc.target/i386/sse-22.c: Ditto. > * gcc.target/i386/sse-23.c: Ditto. > * gcc.target/i386/avx10v1aux-1b.c: New test. > > Co-authored-by: Venkataramanan Kumar > <[email protected]> > --- > gcc/config/i386/avx10v1auxintrin.h | 469 ++++++++++++++++++ > gcc/testsuite/g++.dg/other/i386-2.C | 2 +- > gcc/testsuite/g++.dg/other/i386-3.C | 2 +- > gcc/testsuite/gcc.target/i386/avx-1.c | 2 +- > gcc/testsuite/gcc.target/i386/avx10v1aux-1b.c | 274 ++++++++++ > gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + > gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- > gcc/testsuite/gcc.target/i386/sse-13.c | 2 +- > gcc/testsuite/gcc.target/i386/sse-14.c | 2 +- > gcc/testsuite/gcc.target/i386/sse-22.c | 2 +- > gcc/testsuite/gcc.target/i386/sse-23.c | 2 +- > 11 files changed, 753 insertions(+), 8 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/avx10v1aux-1b.c > > diff --git a/gcc/config/i386/avx10v1auxintrin.h > b/gcc/config/i386/avx10v1auxintrin.h > index 6653d32d5bc..b2c30f9fe4a 100644 > --- a/gcc/config/i386/avx10v1auxintrin.h > +++ b/gcc/config/i386/avx10v1auxintrin.h > @@ -851,6 +851,475 @@ > (__mmask32) U, > \ > R) > > +#define _mm_mask_dpbssd_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpbssd_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpbssd_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpbssd_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_mask_dpbssds_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpbssds_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpbssds_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpbssds_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_mask_dpbsud_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpbsud_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpbsud_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpbsud_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_mask_dpbsuds_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpbsuds_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpbsuds_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpbsuds_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_mask_dpbuud_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpbuud_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpbuud_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpbuud_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_mask_dpbuuds_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpbuuds_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpbuuds_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpbuuds_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpbssd_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpbssd_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpbssd_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpbssd_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpbssds_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpbssds_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpbssds_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpbssds_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpbsud_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpbsud_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpbsud_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpbsud_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpbsuds_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpbsuds_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpbsuds_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpbsuds_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpbuud_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpbuud_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpbuud_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpbuud_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpbuuds_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpbuuds_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpbuuds_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpbuuds_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm512_dpbssd_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbssd512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpbssd_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpbssd_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpbssd_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbssd_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_dpbssds_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbssds512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpbssds_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpbssds_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpbssds_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbssds_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_dpbsud_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbsud512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpbsud_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpbsud_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpbsud_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbsud_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_dpbsuds_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbsuds512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpbsuds_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpbsuds_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpbsuds_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbsuds_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_dpbuud_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbuud512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpbuud_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpbuud_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpbuud_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbuud_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_dpbuuds_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbuuds512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpbuuds_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpbuuds_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpbuuds_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpbuuds_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm_mask_dpwsud_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpwsud_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpwsud_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpwsud_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_mask_dpwsuds_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpwsuds_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpwsuds_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpwsuds_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_mask_dpwusd_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpwusd_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpwusd_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpwusd_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_mask_dpwusds_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpwusds_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpwusds_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpwusds_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_mask_dpwuud_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpwuud_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpwuud_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpwuud_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_mask_dpwuuds_epi32(W, U, A, B) \ > + (__m128i) __builtin_ia32_vpdpwuuds_v4si_mask ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm_maskz_dpwuuds_epi32(U, W, A, B) \ > + (__m128i) __builtin_ia32_vpdpwuuds_v4si_maskz ((__v4si) W, \ > + (__v4si) A, \ > + (__v4si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpwsud_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpwsud_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpwsud_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpwsud_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpwsuds_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpwsuds_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpwsuds_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpwsuds_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpwusd_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpwusd_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpwusd_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpwusd_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpwusds_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpwusds_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpwusds_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpwusds_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpwuud_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpwuud_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > + > +#define _mm256_maskz_dpwuud_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpwuud_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_mask_dpwuuds_epi32(W, U, A, B) \ > + (__m256i) __builtin_ia32_vpdpwuuds_v8si_mask ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm256_maskz_dpwuuds_epi32(U, W, A, B) \ > + (__m256i) __builtin_ia32_vpdpwuuds_v8si_maskz ((__v8si) W, \ > + (__v8si) A, \ > + (__v8si) B, \ > + (__mmask8) U) > + > +#define _mm512_dpwsud_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwsud512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpwsud_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpwsud_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpwsud_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwsud_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_dpwsuds_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwsuds512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpwsuds_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpwsuds_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpwsuds_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwsuds_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_dpwusd_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwusd512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpwusd_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpwusd_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpwusd_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwusd_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_dpwusds_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwusds512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpwusds_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpwusds_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpwusds_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwusds_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_dpwuud_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwuud512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpwuud_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpwuud_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpwuud_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwuud_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_dpwuuds_epi32(W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwuuds512 ((__v16si) W, (__v16si) A, > (__v16si) B) > + > +#define _mm512_mask_dpwuuds_epi32(W, U, A, B) \ > + (__m512i) __builtin_ia32_vpdpwuuds_v16si_mask ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > +#define _mm512_maskz_dpwuuds_epi32(U, W, A, B) \ > + (__m512i) __builtin_ia32_vpdpwuuds_v16si_maskz ((__v16si) W, \ > + (__v16si) A, \ > + (__v16si) B, \ > + (__mmask16) U) > + > #ifdef __DISABLE_AVX10V1AUX__ > #undef __DISABLE_AVX10V1AUX__ > #pragma GCC pop_options > diff --git a/gcc/testsuite/g++.dg/other/i386-2.C > b/gcc/testsuite/g++.dg/other/i386-2.C > index d0c6f9990db..115e1eb815e 100644 > --- a/gcc/testsuite/g++.dg/other/i386-2.C > +++ b/gcc/testsuite/g++.dg/other/i386-2.C > @@ -1,5 +1,5 @@ > /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ > -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx - > mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi - > mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed - > mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt - > mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig - > mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx- > tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma - > mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi - > mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 - > mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux > -macev1" } */ > +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx - > mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi - > mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed - > mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt - > mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig - > mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx- > tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma - > mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi - > mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 - > mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux > -macev1 -mavx10v1aux" } */ > /* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib > } } */ > > /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, > diff --git a/gcc/testsuite/g++.dg/other/i386-3.C > b/gcc/testsuite/g++.dg/other/i386-3.C > index f879c489ac8..e1962b349cb 100644 > --- a/gcc/testsuite/g++.dg/other/i386-3.C > +++ b/gcc/testsuite/g++.dg/other/i386-3.C > @@ -1,5 +1,5 @@ > /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ > -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow - > mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt - > mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm - > mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves - > mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni - > mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize - > mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni - > mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 - > mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 - > msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs - > mavx10v2aux -macev1" } */ > +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow - > mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt - > mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm - > mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves - > mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni - > mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize - > mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni - > mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 - > mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 - > msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs - > mavx10v2aux -macev1 -mavx10v1aux" } */ > /* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib > } } */ > > /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, > diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c > b/gcc/testsuite/gcc.target/i386/avx-1.c > index 7a8e5cc2301..10f11c2d1f8 100644 > --- a/gcc/testsuite/gcc.target/i386/avx-1.c > +++ b/gcc/testsuite/gcc.target/i386/avx-1.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 - > m3dnow -mavx -mavx2 -maes -mpclmul -mgfni -mprefetchi -mavx10.2 - > mmovrs -mavx10v2aux -macev1" } */ > +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 - > m3dnow -mavx -mavx2 -maes -mpclmul -mgfni -mprefetchi -mavx10.2 - > mmovrs -mavx10v2aux -macev1 -mavx10v1aux" } */ > /* { dg-add-options bind_pic_locally } */ > > #include <mm_malloc.h> > diff --git a/gcc/testsuite/gcc.target/i386/avx10v1aux-1b.c > b/gcc/testsuite/gcc.target/i386/avx10v1aux-1b.c > new file mode 100644 > index 00000000000..f5eff3973e8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/avx10v1aux-1b.c > @@ -0,0 +1,274 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mavx10v1aux -O2 " } */ > +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssd\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbssds\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0- > 9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0- > 9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbsuds\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpbuud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0- > 9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0- > 9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0- > 9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0- > 9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0- > 9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpbuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0- > 9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0- > 9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwsuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0- > 9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0- > 9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0- > 9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0- > 9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0- > 9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwusds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwusds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0- > 9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwusds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0- > 9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwusds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwusds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0- > 9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwusds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0- > 9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwusds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwusds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0- > 9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwusds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0- > 9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%zmm\[0- > 9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%ymm\[0- > 9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%xmm\[0- > 9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1- > 7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0- > 9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0- > 9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwuuds\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0- > 9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0- > 9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0- > 9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0- > 9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0- > 9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0- > 9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ > +/* { dg-final { scan-assembler-times > "vpdpwuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0- > 9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ > + > +#include <immintrin.h> > + > +volatile __m512 a1; > +volatile __m512h b1,c1; > +volatile __m512i x1,y2,z1; > +volatile __m256 a; > +volatile __m256h b,c; > +volatile __m256i x,y,z; > +volatile __m128 a_; > +volatile __m128h b_,c_; > +volatile __m128i x_,y_,z_; > +volatile __mmask32 m32; > +volatile __mmask16 m16; > +volatile __mmask8 m; > + > +void extern > +avx10v1aux_test (void) > +{ > + x1 = _mm512_dpbssd_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpbssd_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpbssd_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpbssd_epi32 (x, y, z); > + x = _mm256_mask_dpbssd_epi32 (x, m, y, z); > + x = _mm256_maskz_dpbssd_epi32 (m, x, y, z); > + > + x_ = _mm_dpbssd_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpbssd_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpbssd_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpbssds_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpbssds_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpbssds_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpbssds_epi32 (x, y, z); > + x = _mm256_mask_dpbssds_epi32 (x, m, y, z); > + x = _mm256_maskz_dpbssds_epi32 (m, x, y, z); > + > + x_ = _mm_dpbssds_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpbssds_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpbssds_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpbsud_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpbsud_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpbsud_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpbsud_epi32 (x, y, z); > + x = _mm256_mask_dpbsud_epi32 (x, m, y, z); > + x = _mm256_maskz_dpbsud_epi32 (m, x, y, z); > + > + x_ = _mm_dpbsud_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpbsud_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpbsud_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpbsuds_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpbsuds_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpbsuds_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpbsuds_epi32 (x, y, z); > + x = _mm256_mask_dpbsuds_epi32 (x, m, y, z); > + x = _mm256_maskz_dpbsuds_epi32 (m, x, y, z); > + > + x_ = _mm_dpbsuds_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpbsuds_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpbsuds_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpbuud_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpbuud_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpbuud_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpbuud_epi32 (x, y, z); > + x = _mm256_mask_dpbuud_epi32 (x, m, y, z); > + x = _mm256_maskz_dpbuud_epi32 (m, x, y, z); > + > + x_ = _mm_dpbuud_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpbuud_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpbuud_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpbuuds_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpbuuds_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpbuuds_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpbuuds_epi32 (x, y, z); > + x = _mm256_mask_dpbuuds_epi32 (x, m, y, z); > + x = _mm256_maskz_dpbuuds_epi32 (m, x, y, z); > + > + x_ = _mm_dpbuuds_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpbuuds_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpbuuds_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpwsud_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpwsud_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpwsud_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpwsud_epi32 (x, y, z); > + x = _mm256_mask_dpwsud_epi32 (x, m, y, z); > + x = _mm256_maskz_dpwsud_epi32 (m, x, y, z); > + > + x_ = _mm_dpwsud_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpwsud_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpwsud_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpwsuds_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpwsuds_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpwsuds_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpwsuds_epi32 (x, y, z); > + x = _mm256_mask_dpwsuds_epi32 (x, m, y, z); > + x = _mm256_maskz_dpwsuds_epi32 (m, x, y, z); > + > + x_ = _mm_dpwsuds_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpwsuds_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpwsuds_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpwusd_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpwusd_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpwusd_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpwusd_epi32 (x, y, z); > + x = _mm256_mask_dpwusd_epi32 (x, m, y, z); > + x = _mm256_maskz_dpwusd_epi32 (m, x, y, z); > + > + x_ = _mm_dpwusd_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpwusd_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpwusd_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpwusds_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpwusds_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpwusds_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpwusds_epi32 (x, y, z); > + x = _mm256_mask_dpwusds_epi32 (x, m, y, z); > + x = _mm256_maskz_dpwusds_epi32 (m, x, y, z); > + > + x_ = _mm_dpwusds_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpwusds_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpwusds_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpwuud_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpwuud_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpwuud_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpwuud_epi32 (x, y, z); > + x = _mm256_mask_dpwuud_epi32 (x, m, y, z); > + x = _mm256_maskz_dpwuud_epi32 (m, x, y, z); > + > + x_ = _mm_dpwuud_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpwuud_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpwuud_epi32 (m, x_, y_, z_); > + > + x1 = _mm512_dpwuuds_epi32 (x1, y2, z1); > + x1 = _mm512_mask_dpwuuds_epi32 (x1, m16, y2, z1); > + x1 = _mm512_maskz_dpwuuds_epi32 (m16, x1, y2, z1); > + > + x = _mm256_dpwuuds_epi32 (x, y, z); > + x = _mm256_mask_dpwuuds_epi32 (x, m, y, z); > + x = _mm256_maskz_dpwuuds_epi32 (m, x, y, z); > + > + x_ = _mm_dpwuuds_epi32 (x_, y_, z_); > + x_ = _mm_mask_dpwuuds_epi32 (x_, m, y_, z_); > + x_ = _mm_maskz_dpwuuds_epi32 (m, x_, y_, z_); > + > +} > diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc > b/gcc/testsuite/gcc.target/i386/funcspec-56.inc > index f1877802575..0a364ff43d3 100644 > --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc > +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc > @@ -94,6 +94,7 @@ extern void test_movrs (void) > __attribute__((__target__("movrs"))); > extern void test_amx_movrs (void) > __attribute__((__target__("amx-movrs"))); > extern void test_avx10v2aux (void) > __attribute__((__target__("avx10v2aux"))); > extern void test_acev1 (void) > __attribute__((__target__("acev1"))); > +extern void test_avx10v1aux (void) > __attribute__((__target__("avx10v1aux"))); > > extern void test_no_sgx (void) > __attribute__((__target__("no-sgx"))); > extern void test_no_avx512vpopcntdq(void) > __attribute__((__target__("no-avx512vpopcntdq"))); > @@ -189,6 +190,7 @@ extern void test_no_movrs (void) > __attribute__((__target__("no-movrs"))); > extern void test_no_amx_movrs (void) > __attribute__((__target__("no-amx-movrs"))); > extern void test_no_avx10v2aux (void) > __attribute__((__target__("no-avx10v2aux"))); > extern void test_no_acev1 (void) > __attribute__((__target__("no-acev1"))); > +extern void test_no_avx10v1aux (void) > __attribute__((__target__("no-avx10v1aux"))); > > extern void test_arch_nocona (void) > __attribute__((__target__("arch=nocona"))); > extern void test_arch_core2 (void) > __attribute__((__target__("arch=core2"))); > diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c > b/gcc/testsuite/gcc.target/i386/sse-12.c > index 7d8cb38b561..66c49ecff4b 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-12.c > +++ b/gcc/testsuite/gcc.target/i386/sse-12.c > @@ -3,7 +3,7 @@ > popcntintrin.h gfniintrin.h and mm_malloc.h are usable > with -O -std=c89 -pedantic-errors. */ > /* { dg-do compile } */ > -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow - > mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt - > mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm - > mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves - > mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni - > mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize - > mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni - > mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx- > complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512 > -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1" } */ > +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow > -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt - > mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm - > mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves - > mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni - > mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize - > mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni - > mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx- > complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512 > -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10v1aux" } > */ > > #include <x86intrin.h> > > diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c > b/gcc/testsuite/gcc.target/i386/sse-13.c > index 3284fcd4bd4..9bc514c18bc 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-13.c > +++ b/gcc/testsuite/gcc.target/i386/sse-13.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 - > msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt - > mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c - > mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec - > mxsaves -mclflushopt -mavx512vp2intersect -mclwb -mmwaitx -mclzero - > mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mserialize - > mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni - > mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 - > mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 - > msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs - > mavx10v2aux -macev1" } */ > +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 - > msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt - > mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c - > mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec - > mxsaves -mclflushopt -mavx512vp2intersect -mclwb -mmwaitx -mclzero - > mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mserialize - > mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni - > mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 - > mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 - > msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs - > mavx10v2aux -macev1 -mavx10v1aux" } */ > /* { dg-add-options bind_pic_locally } */ > > #include <mm_malloc.h> > diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c > b/gcc/testsuite/gcc.target/i386/sse-14.c > index 1e9ad6bdcf9..93d6baf8c0b 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-14.c > +++ b/gcc/testsuite/gcc.target/i386/sse-14.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 - > msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt - > mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c - > mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec - > mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid - > mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize - > mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni - > mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx- > complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512 > -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1" } */ > +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 - > msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt - > mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c - > mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec - > mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid - > mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize - > mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni - > mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx- > complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512 > -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10v1aux" } > */ > /* { dg-add-options bind_pic_locally } */ > > #include <mm_malloc.h> > diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c > b/gcc/testsuite/gcc.target/i386/sse-22.c > index 9e50994946c..e3b7eea3117 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-22.c > +++ b/gcc/testsuite/gcc.target/i386/sse-22.c > @@ -119,7 +119,7 @@ > > > #ifndef DIFFERENT_PRAGMAS > -#pragma GCC target > ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tb > m,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx5 > 12vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx- > bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx- > fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx- > avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1") > +#pragma GCC target > ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tb > m,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx5 > 12vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx- > bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx- > fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx- > avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10v1aux") > #endif > > /* Following intrinsics require immediate arguments. They > diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c > b/gcc/testsuite/gcc.target/i386/sse-23.c > index c6cf53b5ed0..95ab5c4adf1 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-23.c > +++ b/gcc/testsuite/gcc.target/i386/sse-23.c > @@ -923,6 +923,6 @@ > #define __builtin_ia32_top4mxbssps(W, A, B, C) __builtin_ia32_top4mxbssps > (1, A, B, 9) > #endif > > -#pragma GCC target > ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tb > m,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsav > ec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfi > g,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx- > int8,amx- > bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx- > fp16,prefetchi,raoint,amx- > complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx- > fp8,movrs,amx-movrs,avx10v2aux,acev1") > +#pragma GCC target > ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tb > m,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsav > ec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfi > g,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx- > int8,amx- > bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx- > fp16,prefetchi,raoint,amx- > complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx- > fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10v1aux") > > #include <x86intrin.h> > -- > 2.34.1
