AMD General Hi,
> -----Original Message----- > From: Jiang, Haochen <[email protected]> > Sent: 12 October 2026 12:03 > To: Sharma, Dipesh <[email protected]>; [email protected] > Cc: [email protected]; Liu, Hongtao <[email protected]>; > [email protected]; Kumar, Venkataramanan > <[email protected]> > Subject: RE: [PATCH 1/4] Initial support for AVX10V1AUX > > Caution: This message originated from an External Source. Use proper caution > when opening attachments, clicking links, or responding. > > > > From: Dipesh Sharma <[email protected]> > > Sent: Wednesday, September 23, 2026 7:05 PM > > diff --git a/gcc/common/config/i386/cpuinfo.h > > b/gcc/common/config/i386/cpuinfo.h > > index a689afabd3d..7adcd345a2f 100644 > > --- a/gcc/common/config/i386/cpuinfo.h > > +++ b/gcc/common/config/i386/cpuinfo.h > > @@ -1152,13 +1152,21 @@ get_available_features (struct > > __processor_model *cpu_model, > > set_feature (FEATURE_AVX10V2AUX); > > avx10v2aux_set = 1; > > } > > + if (ecx & bit_AVX10V1AUX) > > + { > > + set_feature (FEATURE_AVX10V1AUX); > > + avx10v1aux_set = 1; > > + } > > } > > } > > > > /* Get Advanced Features at level 0x1d (eax = 0x1d). > > ACE check must be put after AVX10 check to get AVX10 features. > > TODO: Change the condition after AVX10V1AUX is added. */ > > You could remove this TODO line after the change. Okay. > > > - if (version >= 2 && avx10v2aux_set && ace_set && max_cpuid_level >= > > 0x1d) > > + if (((avx10v1aux_set && version >= 1) || version >= 2) > > + && avx10v2aux_set > > + && ace_set > > + && max_cpuid_level >= 0x1d) > > { > > __cpuid_count (0x1d, 0, eax, ebx, ecx, edx); > > if (eax == 2) > > diff --git a/gcc/common/config/i386/i386-common.cc > > b/gcc/common/config/i386/i386-common.cc > > index ed126f4c70d..016e35c2248 100644 > > --- a/gcc/common/config/i386/i386-common.cc > > +++ b/gcc/common/config/i386/i386-common.cc > > @@ -141,7 +141,10 @@ along with GCC; see the file COPYING3. If not see > > #define OPTION_MASK_ISA2_AVX10V2AUX_SET \ > > (OPTION_MASK_ISA2_AVX10_1_SET | > OPTION_MASK_ISA2_AVX10V2AUX) > > #define OPTION_MASK_ISA2_ACEV1_SET \ > > - (OPTION_MASK_ISA2_AVX10V2AUX_SET | OPTION_MASK_ISA2_ACEV1) > > + (OPTION_MASK_ISA2_AVX10V2AUX_SET | > OPTION_MASK_ISA2_AVX10V1AUX_SET \ > > + | OPTION_MASK_ISA2_ACEV1) > > I lean not to set AVX10V1AUX since it is AVX10V1AUX or AVX10.2 here. Ok. > > > +#define OPTION_MASK_ISA2_AVX10V1AUX_SET \ > > + (OPTION_MASK_ISA2_AVX10_1_SET | > OPTION_MASK_ISA2_AVX10V1AUX) > > > > /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same > > as -msse4.2. */ > > @@ -336,8 +339,10 @@ along with GCC; see the file COPYING3. If not see > > #define OPTION_MASK_ISA2_AMX_MOVRS_UNSET > OPTION_MASK_ISA2_AMX_MOVRS > > #define OPTION_MASK_ISA2_AVX512BMM_UNSET > OPTION_MASK_ISA2_AVX512BMM > > #define OPTION_MASK_ISA2_AVX10V2AUX_UNSET \ > > - (OPTION_MASK_ISA2_AVX10V2AUX | > OPTION_MASK_ISA2_ACEV1_UNSET) > > + (OPTION_MASK_ISA2_ACEV1_UNSET | > OPTION_MASK_ISA2_AVX10V2AUX) > > Why would you touch this line? It is the same. I'll revert it. > > > > #define OPTION_MASK_ISA2_ACEV1_UNSET OPTION_MASK_ISA2_ACEV1 > > +#define OPTION_MASK_ISA2_AVX10V1AUX_UNSET \ > > + (OPTION_MASK_ISA2_ACEV1_UNSET | > OPTION_MASK_ISA2_AVX10V1AUX) > > And please do not unset ACEv1 when no-avx10v1aux. It will lead to > those platforms w/ AVX10.2 and ACEv1 but w/o AVX10V1AUX wrongly > disabling ACEv1. Ok. > > > > > /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same > > as -mno-sse4.1. */ > > diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h > > index c40970df872..e126bc72d54 100644 > > --- a/gcc/config/i386/cpuid.h > > +++ b/gcc/config/i386/cpuid.h > > @@ -174,6 +174,7 @@ > > /* AVX10 sub leaf (%eax == 0x24, %ecx == 1) */ > > /* %ecx */ > > #define bit_AVX10V2AUX (1 << 3) > > +#define bit_AVX10V1AUX (1 << 2) > > Please put them in order according to the number It shifts, > i.e., put AVX10V1AUX before AVX10V2AUX here. Ok. Thanks, Dipesh
