In this patch, we will first add initial support
for AVX10V1AUX.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features): Add AVX10V1AUX.
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10V1AUX_SET):
New.
(OPTION_MASK_ISA2_AVX10_1_UNSET): Disable AVX10V1AUX.
(OPTION_MASK_ISA2_AVX10V2AUX_UNSET): Disable ACEV1.
(OPTION_MASK_ISA2_AVX10V1AUX_UNSET): Disable ACEV1.
(ix86_handle_option): Handle AVX10V1AUX.
* common/config/i386/i386-cpuinfo.h (enum processor_features): Add
FEATURE_AVX10V1AUX.
* common/config/i386/i386-isas.h: Handle avx10v1aux.
* config/i386/cpuid.h (bit_AVX10V1AUX): New.
* config/i386/i386-c.cc (ix86_target_macros_internal): Handle
avx10v1aux.
* config/i386/i386-isa.def (AVX10V1AUX): New.
* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
Handle Ditto..
* config/i386/i386.opt: Add avx10v1aux.
* config/i386/i386.opt.urls: Regenerated.
* doc/extend.texi: Add avx10v1aux documentation.
* doc/invoke.texi: Ditto.
* doc/sourcebuild.texi: Ditto.
Co-authored-by: Venkataramanan Kumar <[email protected]>
---
gcc/common/config/i386/cpuinfo.h | 12 ++++++++++--
gcc/common/config/i386/i386-common.cc | 26 +++++++++++++++++++++++---
gcc/common/config/i386/i386-cpuinfo.h | 1 +
gcc/common/config/i386/i386-isas.h | 2 ++
gcc/config/i386/cpuid.h | 1 +
gcc/config/i386/i386-c.cc | 2 ++
gcc/config/i386/i386-isa.def | 1 +
gcc/config/i386/i386-options.cc | 4 +++-
gcc/config/i386/i386.opt | 5 +++++
gcc/config/i386/i386.opt.urls | 3 +++
gcc/doc/extend.texi | 5 +++++
gcc/doc/invoke.texi | 8 +++++++-
gcc/doc/sourcebuild.texi | 3 +++
13 files changed, 66 insertions(+), 7 deletions(-)
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index a689afabd3d..7adcd345a2f 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -826,7 +826,7 @@ get_available_features (struct __processor_model *cpu_model,
int has_kl = 0;
/* Record AVX10 version. */
int avx10_set = 0;
- int ace_set = 0, avx10v2aux_set = 0;
+ int ace_set = 0, avx10v2aux_set = 0, avx10v1aux_set = 0;
int version = 0;
if ((ecx & bit_OSXSAVE))
{
@@ -1152,13 +1152,21 @@ get_available_features (struct __processor_model
*cpu_model,
set_feature (FEATURE_AVX10V2AUX);
avx10v2aux_set = 1;
}
+ if (ecx & bit_AVX10V1AUX)
+ {
+ set_feature (FEATURE_AVX10V1AUX);
+ avx10v1aux_set = 1;
+ }
}
}
/* Get Advanced Features at level 0x1d (eax = 0x1d).
ACE check must be put after AVX10 check to get AVX10 features.
TODO: Change the condition after AVX10V1AUX is added. */
- if (version >= 2 && avx10v2aux_set && ace_set && max_cpuid_level >= 0x1d)
+ if (((avx10v1aux_set && version >= 1) || version >= 2)
+ && avx10v2aux_set
+ && ace_set
+ && max_cpuid_level >= 0x1d)
{
__cpuid_count (0x1d, 0, eax, ebx, ecx, edx);
if (eax == 2)
diff --git a/gcc/common/config/i386/i386-common.cc
b/gcc/common/config/i386/i386-common.cc
index ed126f4c70d..016e35c2248 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -141,7 +141,10 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AVX10V2AUX_SET \
(OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10V2AUX)
#define OPTION_MASK_ISA2_ACEV1_SET \
- (OPTION_MASK_ISA2_AVX10V2AUX_SET | OPTION_MASK_ISA2_ACEV1)
+ (OPTION_MASK_ISA2_AVX10V2AUX_SET | OPTION_MASK_ISA2_AVX10V1AUX_SET \
+ | OPTION_MASK_ISA2_ACEV1)
+#define OPTION_MASK_ISA2_AVX10V1AUX_SET \
+ (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10V1AUX)
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
@@ -328,7 +331,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
#define OPTION_MASK_ISA2_AVX10_1_UNSET \
(OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET \
- | OPTION_MASK_ISA2_AVX10V2AUX_UNSET)
+ | OPTION_MASK_ISA2_AVX10V2AUX_UNSET | OPTION_MASK_ISA2_AVX10V1AUX_UNSET)
#define OPTION_MASK_ISA2_AVX10_2_UNSET OPTION_MASK_ISA2_AVX10_2
#define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
#define OPTION_MASK_ISA2_AMX_FP8_UNSET OPTION_MASK_ISA2_AMX_FP8
@@ -336,8 +339,10 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS
#define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM
#define OPTION_MASK_ISA2_AVX10V2AUX_UNSET \
- (OPTION_MASK_ISA2_AVX10V2AUX | OPTION_MASK_ISA2_ACEV1_UNSET)
+ (OPTION_MASK_ISA2_ACEV1_UNSET | OPTION_MASK_ISA2_AVX10V2AUX)
#define OPTION_MASK_ISA2_ACEV1_UNSET OPTION_MASK_ISA2_ACEV1
+#define OPTION_MASK_ISA2_AVX10V1AUX_UNSET \
+ (OPTION_MASK_ISA2_ACEV1_UNSET | OPTION_MASK_ISA2_AVX10V1AUX)
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
@@ -1437,6 +1442,21 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_mavx10v1aux:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10V1AUX_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10V1AUX_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10V1AUX_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10V1AUX_UNSET;
+ }
+ return true;
+
case OPT_mamx_avx512:
if (value)
{
diff --git a/gcc/common/config/i386/i386-cpuinfo.h
b/gcc/common/config/i386/i386-cpuinfo.h
index ed989667e02..e75b18bda22 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -285,6 +285,7 @@ enum processor_features
FEATURE_AVX512BMM,
FEATURE_AVX10V2AUX,
FEATURE_ACEV1,
+ FEATURE_AVX10V1AUX,
CPU_FEATURE_MAX
};
diff --git a/gcc/common/config/i386/i386-isas.h
b/gcc/common/config/i386/i386-isas.h
index 171226ab07b..f4a9fbad6bf 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -194,4 +194,6 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("avx10v2aux", FEATURE_AVX10V2AUX, P_NONE,
"-mavx10v2aux")
ISA_NAMES_TABLE_ENTRY("acev1", FEATURE_ACEV1, P_NONE, "-macev1")
+ ISA_NAMES_TABLE_ENTRY("avx10v1aux", FEATURE_AVX10V1AUX, P_NONE,
+ "-mavx10v1aux")
ISA_NAMES_TABLE_END
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index c40970df872..e126bc72d54 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -174,6 +174,7 @@
/* AVX10 sub leaf (%eax == 0x24, %ecx == 1) */
/* %ecx */
#define bit_AVX10V2AUX (1 << 3)
+#define bit_AVX10V1AUX (1 << 2)
/* AMX sub leaf (%eax == 0x1e, %ecx == 1) */
/* %eax */
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index f6a4093c277..6750332ee9c 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -794,6 +794,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__AVX10V2AUX__");
if (isa_flag2 & OPTION_MASK_ISA2_ACEV1)
def_or_undef (parse_in, "__ACEV1__");
+ if (isa_flag2 & OPTION_MASK_ISA2_AVX10V1AUX)
+ def_or_undef (parse_in, "__AVX10V1AUX__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index 28835b1d542..9803ad6b6f1 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -127,3 +127,4 @@ DEF_PTA(AMX_MOVRS)
DEF_PTA(AVX512BMM)
DEF_PTA(AVX10V2AUX)
DEF_PTA(ACEV1)
+DEF_PTA(AVX10V1AUX)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 37bb75a75c2..bef86229ed6 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -276,7 +276,8 @@ static struct ix86_target_opts isa2_opts[] =
{ "-mamx-movrs", OPTION_MASK_ISA2_AMX_MOVRS },
{ "-mavx512bmm", OPTION_MASK_ISA2_AVX512BMM },
{ "-mavx10v2aux", OPTION_MASK_ISA2_AVX10V2AUX },
- { "-macev1", OPTION_MASK_ISA2_ACEV1 }
+ { "-macev1", OPTION_MASK_ISA2_ACEV1 },
+ { "-mavx10v1aux", OPTION_MASK_ISA2_AVX10V1AUX }
};
static struct ix86_target_opts isa_opts[] =
{
@@ -1143,6 +1144,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree
args, char *p_strings[],
IX86_ATTR_ISA ("avx512bmm", OPT_mavx512bmm),
IX86_ATTR_ISA ("avx10v2aux", OPT_mavx10v2aux),
IX86_ATTR_ISA ("acev1", OPT_macev1),
+ IX86_ATTR_ISA ("avx10v1aux", OPT_mavx10v1aux),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index f9aeeac08fa..740a08f8075 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1399,3 +1399,8 @@ macev1
Target Mask(ISA2_ACEV1) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
AVX10.1 and ACEV1 built-in functions and code generation.
+
+mavx10v1aux
+Target Mask(ISA2_AVX10V1AUX) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+AVX10.1 and AVX10V1AUX built-in functions and code generation.
diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index 5cfa30c07e3..304cd67c5aa 100644
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -641,3 +641,6 @@ UrlSuffix(gcc/x86-Options.html#index-mavx10v2aux)
macev1
UrlSuffix(gcc/x86-Options.html#index-macev1)
+mavx10v1aux
+UrlSuffix(gcc/x86-Options.html#index-mavx10v1aux)
+
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index a4981eb0deb..c829ce4adfd 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9571,6 +9571,11 @@ Enable/disable the generation of the AVX10V2AUX
instructions.
@itemx no-acev1
Enable/disable the generation of the ACEV1 instructions.
+@atindex @code{target("avx10v1aux")}, x86
+@item avx10v1aux
+@itemx no-avx10v1aux
+Enable/disable the generation of the AVX10V1AUX instructions.
+
@atindex @code{target("cld")}, x86
@item cld
@itemx no-cld
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 86a00df78cf..4f4245c73b0 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1553,7 +1553,7 @@ See RS/6000 and PowerPC Options.
-mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
-musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mmovrs -mamx-movrs
--mavx512bmm -mavx10v2aux -macev1
+-mavx512bmm -mavx10v2aux -macev1 -mavx10v1aux
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@@ -36315,6 +36315,12 @@ AVX10.1 and AVX10V2AUX built-in functions and code
generation.
@item -macev1
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
AVX10.1 and ACEV1 built-in functions and code generation.
+
+@opindex mavx10v1aux
+@opindex mno-avx10v1aux
+@item -mavx10v1aux
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+AVX10.1 and AVX10V1AUX built-in functions and code generation.
@end table
These additional options are available for the x86 processor family.
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index b02cb28db51..50201436a89 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2718,6 +2718,9 @@ Target supports the execution of @code{avx} instructions.
@item avx10v2aux
Target supports the execution of @code{avx10v2aux} instructions.
+@item avx10v1aux
+Target supports the execution of @code{avx10v1aux} instructions.
+
@item avx10.1
Target supports the execution of @code{avx10.1} instructions.
--
2.34.1
