> On 2011-12-20 01:16:59, Gabe Black wrote: > > src/cpu/CheckerCPU.py, line 38 > > <http://reviews.m5sim.org/r/910/diff/3/?file=16271#file16271line38> > > > > What's your reasoning for changing this? Are you worried that this is > > likely to happen but not signify a real bug? Have you actually seen that > > happen?
Yes. I see loads from the Checker complain that the values don't match often enough due to no LSQ snooping. I think setting warnOnlyOnLoadError to False should be the default. Functional LSQ snooping from the Checker should be added as a future task to figure out a way around this. In FS mode, it is also possible for loads from the Checker to see different values than the O3 because of coherent IO as well. > On 2011-12-20 01:16:59, Gabe Black wrote: > > src/cpu/base.cc, line 420 > > <http://reviews.m5sim.org/r/910/diff/3/?file=16274#file16274line420> > > > > Have you tested how the checker acts when you switch CPUs? It wouldn't > > be criminal if that isn't working perfectly at this stage since this change > > already fixing alot, but it would be nice if that worked. The Checker works with fast-forwarding and checkpoints and has been tested. > On 2011-12-20 01:16:59, Gabe Black wrote: > > src/cpu/o3/thread_context_impl.hh, line 335 > > <http://reviews.m5sim.org/r/910/diff/3/?file=16293#file16293line335> > > > > Drop the {}s. I'll stop pointing these out (and I may have missed > > some), but please fix throughout. I'll go through and correct the style in the upcoming days. Thanks for the review comments. - Geoffrey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/910/#review1764 ----------------------------------------------------------- On 2011-12-13 13:25:24, Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/910/ > ----------------------------------------------------------- > > (Updated 2011-12-13 13:25:24) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 > > Brings the CheckerCPU back to a functioning state allowing FS and SE mode > checking of the O3CPU. These changes have only been tested with the > ARM ISA. Other ISAs will potentially require modification. > > > Diffs > ----- > > configs/common/FSConfig.py c1ab57ea8805 > src/arch/arm/isa.cc c1ab57ea8805 > src/arch/arm/isa/insts/m5ops.isa c1ab57ea8805 > src/arch/arm/isa/insts/misc.isa c1ab57ea8805 > src/arch/arm/table_walker.hh c1ab57ea8805 > src/arch/arm/table_walker.cc c1ab57ea8805 > src/arch/arm/tlb.hh c1ab57ea8805 > src/arch/arm/tlb.cc c1ab57ea8805 > src/arch/arm/utility.cc c1ab57ea8805 > src/cpu/BaseCPU.py c1ab57ea8805 > src/cpu/CheckerCPU.py c1ab57ea8805 > src/cpu/DummyChecker.py PRE-CREATION > src/cpu/SConscript c1ab57ea8805 > src/cpu/base.cc c1ab57ea8805 > src/cpu/base_dyn_inst.hh c1ab57ea8805 > src/cpu/base_dyn_inst_impl.hh c1ab57ea8805 > src/cpu/checker/cpu.hh c1ab57ea8805 > src/cpu/checker/cpu.cc c1ab57ea8805 > src/cpu/checker/cpu_impl.hh c1ab57ea8805 > src/cpu/checker/thread_context.hh c1ab57ea8805 > src/cpu/dummy_checker_builder.cc PRE-CREATION > src/cpu/o3/O3CPU.py c1ab57ea8805 > src/cpu/o3/O3Checker.py c1ab57ea8805 > src/cpu/o3/checker_builder.cc c1ab57ea8805 > src/cpu/o3/commit_impl.hh c1ab57ea8805 > src/cpu/o3/cpu.hh c1ab57ea8805 > src/cpu/o3/cpu.cc c1ab57ea8805 > src/cpu/o3/dyn_inst_impl.hh c1ab57ea8805 > src/cpu/o3/fetch_impl.hh c1ab57ea8805 > src/cpu/o3/iew_impl.hh c1ab57ea8805 > src/cpu/o3/lsq_unit_impl.hh c1ab57ea8805 > src/cpu/o3/thread_context.hh c1ab57ea8805 > src/cpu/o3/thread_context_impl.hh c1ab57ea8805 > src/cpu/simple/BaseSimpleCPU.py c1ab57ea8805 > src/cpu/simple/base.hh c1ab57ea8805 > src/cpu/simple/base.cc c1ab57ea8805 > src/cpu/simple_thread.hh c1ab57ea8805 > src/cpu/thread_context.hh c1ab57ea8805 > src/dev/Device.py c1ab57ea8805 > src/dev/isa_fake.hh c1ab57ea8805 > src/dev/isa_fake.cc c1ab57ea8805 > > Diff: http://reviews.m5sim.org/r/910/diff > > > Testing > ------- > > Successfully runs gzip in SE mode. Successfully boots linux kernel in FS > mode. Works with checkpoints and fast-forwarding. Testing with buggy O3CPUs > to test checker's capabilities. > > > Thanks, > > Geoffrey > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
