> On 2012-01-13 08:51:34, Steve Reinhardt wrote: > > Sorry about nagging you on the file renames; it didn't occur to me that > > perhaps you had fixed that and reviewboard just wasn't capable of showing > > it. Also I agree on saving the little things that are carryovers from the > > old code for a separate patch (the comma spacing and the translate() helper > > function); since reviewboard wasn't showing the rename properly it wasn't > > obvious that these issues were also there in the old code. > > > > The one thing I am still concerned about is the read*() and write*() > > methods on FSTranslatingPortProxy. It seems like those aren't necessary > > (since VirtualPort doesn't have them) and the current implementations > > aren't correct (since they don't deal with page crossings), so I'd prefer > > to see those just left out until we put in working ones. In the meantime, > > the even-more-broken PortProxy methods will get inherited and not > > overridden; if we care about that, maybe we should temporarily override > > them with methods that panic. (If we had C++11 we could delete them...)
No problem...I'm getting used to reviewboard oddities :) I see what you are saying about the readGtoH/readHtoG and writeGtoH/writeHtoG and will make an attempt at removing them and see what the outcome is on the regressions. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/943/#review1942 ----------------------------------------------------------- On 2012-01-12 10:19:12, Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/943/ > ----------------------------------------------------------- > > (Updated 2012-01-12 10:19:12) > > > Review request for Default. > > > Summary > ------- > > MEM: Add port proxies instead of non-structural ports > > Port proxies are used to replace non-structural ports, and thus enable > all ports in the system to correspond to a structural entity. This has > the advantage of accessing memory through the normal memory subsystem > and thus allowing any constellation of distributed memories, address > maps, etc. Most accesses are done through the "system port" that is > used for loading binaries, debugging etc. For the entities that belong > to the CPU, e.g. threads and thread contexts, they wrap the CPU data > port in a port proxy. > > The following replacements are made: > FunctionalPort > PortProxy > TranslatingPort > SETranslatingPortProxy > VirtualPort > FSTranslatingPortProxy > > > Diffs > ----- > > configs/common/FSConfig.py 99ba36eaa789 > configs/example/se.py 99ba36eaa789 > configs/ruby/Ruby.py 99ba36eaa789 > src/arch/alpha/freebsd/system.cc 99ba36eaa789 > src/arch/alpha/linux/process.cc 99ba36eaa789 > src/arch/alpha/linux/system.hh 99ba36eaa789 > src/arch/alpha/linux/system.cc 99ba36eaa789 > src/arch/alpha/linux/threadinfo.hh 99ba36eaa789 > src/arch/alpha/remote_gdb.cc 99ba36eaa789 > src/arch/alpha/stacktrace.cc 99ba36eaa789 > src/arch/alpha/system.hh 99ba36eaa789 > src/arch/alpha/system.cc 99ba36eaa789 > src/arch/alpha/tru64/process.cc 99ba36eaa789 > src/arch/alpha/tru64/system.cc 99ba36eaa789 > src/arch/alpha/utility.cc 99ba36eaa789 > src/arch/alpha/vtophys.hh 99ba36eaa789 > src/arch/alpha/vtophys.cc 99ba36eaa789 > src/arch/arm/linux/process.cc 99ba36eaa789 > src/arch/arm/linux/system.cc 99ba36eaa789 > src/arch/arm/process.cc 99ba36eaa789 > src/arch/arm/stacktrace.cc 99ba36eaa789 > src/arch/arm/system.hh 99ba36eaa789 > src/arch/arm/system.cc 99ba36eaa789 > src/arch/arm/utility.cc 99ba36eaa789 > src/arch/arm/vtophys.cc 99ba36eaa789 > src/arch/mips/linux/process.cc 99ba36eaa789 > src/arch/mips/linux/system.cc 99ba36eaa789 > src/arch/mips/linux/threadinfo.hh 99ba36eaa789 > src/arch/mips/stacktrace.cc 99ba36eaa789 > src/arch/mips/utility.cc 99ba36eaa789 > src/arch/power/linux/process.cc 99ba36eaa789 > src/arch/power/process.cc 99ba36eaa789 > src/arch/sparc/linux/syscalls.cc 99ba36eaa789 > src/arch/sparc/process.cc 99ba36eaa789 > src/arch/sparc/solaris/process.cc 99ba36eaa789 > src/arch/sparc/system.hh 99ba36eaa789 > src/arch/sparc/system.cc 99ba36eaa789 > src/arch/sparc/utility.cc 99ba36eaa789 > src/arch/sparc/vtophys.cc 99ba36eaa789 > src/arch/x86/bios/intelmp.hh 99ba36eaa789 > src/arch/x86/bios/intelmp.cc 99ba36eaa789 > src/arch/x86/bios/smbios.hh 99ba36eaa789 > src/arch/x86/bios/smbios.cc 99ba36eaa789 > src/arch/x86/linux/syscalls.cc 99ba36eaa789 > src/arch/x86/linux/system.cc 99ba36eaa789 > src/arch/x86/process.cc 99ba36eaa789 > src/arch/x86/stacktrace.cc 99ba36eaa789 > src/arch/x86/system.cc 99ba36eaa789 > src/base/loader/elf_object.hh 99ba36eaa789 > src/base/loader/elf_object.cc 99ba36eaa789 > src/base/loader/hex_file.hh 99ba36eaa789 > src/base/loader/hex_file.cc 99ba36eaa789 > src/base/loader/object_file.hh 99ba36eaa789 > src/base/loader/object_file.cc 99ba36eaa789 > src/base/remote_gdb.cc 99ba36eaa789 > src/cpu/checker/thread_context.hh 99ba36eaa789 > src/cpu/inorder/cpu.hh 99ba36eaa789 > src/cpu/inorder/cpu.cc 99ba36eaa789 > src/cpu/inorder/resources/cache_unit.hh 99ba36eaa789 > src/cpu/inorder/resources/cache_unit.cc 99ba36eaa789 > src/cpu/inorder/thread_context.hh 99ba36eaa789 > src/cpu/inorder/thread_context.cc 99ba36eaa789 > src/cpu/o3/cpu.hh 99ba36eaa789 > src/cpu/o3/cpu.cc 99ba36eaa789 > src/cpu/o3/lsq.hh 99ba36eaa789 > src/cpu/o3/lsq_impl.hh 99ba36eaa789 > src/cpu/o3/thread_context.hh 99ba36eaa789 > src/cpu/o3/thread_context_impl.hh 99ba36eaa789 > src/cpu/ozone/cpu.hh 99ba36eaa789 > src/cpu/ozone/cpu_impl.hh 99ba36eaa789 > src/cpu/simple/atomic.hh 99ba36eaa789 > src/cpu/simple/atomic.cc 99ba36eaa789 > src/cpu/simple/timing.hh 99ba36eaa789 > src/cpu/simple/timing.cc 99ba36eaa789 > src/cpu/simple_thread.hh 99ba36eaa789 > src/cpu/simple_thread.cc 99ba36eaa789 > src/cpu/thread_context.hh 99ba36eaa789 > src/cpu/thread_state.hh 99ba36eaa789 > src/cpu/thread_state.cc 99ba36eaa789 > src/dev/simple_disk.cc 99ba36eaa789 > src/kern/tru64/tru64.hh 99ba36eaa789 > src/kern/tru64/tru64_events.cc 99ba36eaa789 > src/mem/SConscript 99ba36eaa789 > src/mem/fs_translating_port_proxy.hh PRE-CREATION > src/mem/fs_translating_port_proxy.cc PRE-CREATION > src/mem/port.hh 99ba36eaa789 > src/mem/port_proxy.hh PRE-CREATION > src/mem/port_proxy.cc PRE-CREATION > src/mem/ruby/system/RubyPort.cc 99ba36eaa789 > src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION > src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION > src/mem/ruby/system/SConscript 99ba36eaa789 > src/mem/ruby/system/Sequencer.py 99ba36eaa789 > src/mem/se_translating_port_proxy.hh PRE-CREATION > src/mem/se_translating_port_proxy.cc PRE-CREATION > src/mem/translating_port.hh 99ba36eaa789 > src/mem/translating_port.cc 99ba36eaa789 > src/mem/vport.hh 99ba36eaa789 > src/mem/vport.cc 99ba36eaa789 > src/sim/arguments.hh 99ba36eaa789 > src/sim/process.hh 99ba36eaa789 > src/sim/process.cc 99ba36eaa789 > src/sim/process_impl.hh 99ba36eaa789 > src/sim/syscall_emul.hh 99ba36eaa789 > src/sim/syscall_emul.cc 99ba36eaa789 > src/sim/system.hh 99ba36eaa789 > src/sim/system.cc 99ba36eaa789 > src/sim/vptr.hh 99ba36eaa789 > tests/configs/inorder-timing.py 99ba36eaa789 > tests/configs/memtest-ruby.py 99ba36eaa789 > tests/configs/memtest.py 99ba36eaa789 > tests/configs/o3-timing-mp.py 99ba36eaa789 > tests/configs/o3-timing.py 99ba36eaa789 > tests/configs/rubytest-ruby.py 99ba36eaa789 > tests/configs/simple-atomic-mp.py 99ba36eaa789 > tests/configs/simple-atomic.py 99ba36eaa789 > tests/configs/simple-timing-mp-ruby.py 99ba36eaa789 > tests/configs/simple-timing-mp.py 99ba36eaa789 > tests/configs/simple-timing-ruby.py 99ba36eaa789 > tests/configs/simple-timing.py 99ba36eaa789 > > Diff: http://reviews.m5sim.org/r/943/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
