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(Updated 2012-01-13 10:24:11.388932) Review request for Default. Summary ------- MEM: Add port proxies instead of non-structural ports Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy Diffs (updated) ----- configs/common/FSConfig.py f348cf78072c configs/example/se.py f348cf78072c configs/ruby/Ruby.py f348cf78072c src/arch/alpha/freebsd/system.cc f348cf78072c src/arch/alpha/linux/process.cc f348cf78072c src/arch/alpha/linux/system.hh f348cf78072c src/arch/alpha/linux/system.cc f348cf78072c src/arch/alpha/linux/threadinfo.hh f348cf78072c src/arch/alpha/remote_gdb.cc f348cf78072c src/arch/alpha/stacktrace.cc f348cf78072c src/arch/alpha/system.hh f348cf78072c src/arch/alpha/system.cc f348cf78072c src/arch/alpha/tru64/process.cc f348cf78072c src/arch/alpha/tru64/system.cc f348cf78072c src/arch/alpha/utility.cc f348cf78072c src/arch/alpha/vtophys.hh f348cf78072c src/arch/alpha/vtophys.cc f348cf78072c src/arch/arm/linux/process.cc f348cf78072c src/arch/arm/linux/system.cc f348cf78072c src/arch/arm/process.cc f348cf78072c src/arch/arm/stacktrace.cc f348cf78072c src/arch/arm/system.hh f348cf78072c src/arch/arm/system.cc f348cf78072c src/arch/arm/utility.cc f348cf78072c src/arch/arm/vtophys.cc f348cf78072c src/arch/mips/linux/process.cc f348cf78072c src/arch/mips/linux/system.cc f348cf78072c src/arch/mips/linux/threadinfo.hh f348cf78072c src/arch/mips/stacktrace.cc f348cf78072c src/arch/mips/utility.cc f348cf78072c src/arch/power/linux/process.cc f348cf78072c src/arch/power/process.cc f348cf78072c src/arch/sparc/linux/syscalls.cc f348cf78072c src/arch/sparc/process.cc f348cf78072c src/arch/sparc/solaris/process.cc f348cf78072c src/arch/sparc/system.hh f348cf78072c src/arch/sparc/system.cc f348cf78072c src/arch/sparc/utility.cc f348cf78072c src/arch/sparc/vtophys.cc f348cf78072c src/arch/x86/bios/intelmp.hh f348cf78072c src/arch/x86/bios/intelmp.cc f348cf78072c src/arch/x86/bios/smbios.hh f348cf78072c src/arch/x86/bios/smbios.cc f348cf78072c src/arch/x86/linux/syscalls.cc f348cf78072c src/arch/x86/linux/system.cc f348cf78072c src/arch/x86/process.cc f348cf78072c src/arch/x86/stacktrace.cc f348cf78072c src/arch/x86/system.cc f348cf78072c src/base/loader/elf_object.hh f348cf78072c src/base/loader/elf_object.cc f348cf78072c src/base/loader/hex_file.hh f348cf78072c src/base/loader/hex_file.cc f348cf78072c src/base/loader/object_file.hh f348cf78072c src/base/loader/object_file.cc f348cf78072c src/base/remote_gdb.cc f348cf78072c src/cpu/checker/thread_context.hh f348cf78072c src/cpu/inorder/cpu.hh f348cf78072c src/cpu/inorder/cpu.cc f348cf78072c src/cpu/inorder/resources/cache_unit.hh f348cf78072c src/cpu/inorder/resources/cache_unit.cc f348cf78072c src/cpu/inorder/thread_context.hh f348cf78072c src/cpu/inorder/thread_context.cc f348cf78072c src/cpu/o3/cpu.hh f348cf78072c src/cpu/o3/cpu.cc f348cf78072c src/cpu/o3/lsq.hh f348cf78072c src/cpu/o3/lsq_impl.hh f348cf78072c src/cpu/o3/thread_context.hh f348cf78072c src/cpu/o3/thread_context_impl.hh f348cf78072c src/cpu/ozone/cpu.hh f348cf78072c src/cpu/ozone/cpu_impl.hh f348cf78072c src/cpu/simple/atomic.hh f348cf78072c src/cpu/simple/atomic.cc f348cf78072c src/cpu/simple/timing.hh f348cf78072c src/cpu/simple/timing.cc f348cf78072c src/cpu/simple_thread.hh f348cf78072c src/cpu/simple_thread.cc f348cf78072c src/cpu/thread_context.hh f348cf78072c src/cpu/thread_state.hh f348cf78072c src/cpu/thread_state.cc f348cf78072c src/dev/simple_disk.cc f348cf78072c src/kern/tru64/tru64.hh f348cf78072c src/kern/tru64/tru64_events.cc f348cf78072c src/mem/SConscript f348cf78072c src/mem/fs_translating_port_proxy.hh PRE-CREATION src/mem/fs_translating_port_proxy.cc PRE-CREATION src/mem/port.hh f348cf78072c src/mem/port_impl.hh f348cf78072c src/mem/port_proxy.hh PRE-CREATION src/mem/port_proxy.cc PRE-CREATION src/mem/ruby/system/RubyPort.cc f348cf78072c src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION src/mem/ruby/system/SConscript f348cf78072c src/mem/ruby/system/Sequencer.py f348cf78072c src/mem/se_translating_port_proxy.hh PRE-CREATION src/mem/se_translating_port_proxy.cc PRE-CREATION src/mem/translating_port.hh f348cf78072c src/mem/translating_port.cc f348cf78072c src/mem/vport.hh f348cf78072c src/mem/vport.cc f348cf78072c src/sim/arguments.hh f348cf78072c src/sim/process.hh f348cf78072c src/sim/process.cc f348cf78072c src/sim/process_impl.hh f348cf78072c src/sim/syscall_emul.hh f348cf78072c src/sim/syscall_emul.cc f348cf78072c src/sim/system.hh f348cf78072c src/sim/system.cc f348cf78072c src/sim/vptr.hh f348cf78072c tests/configs/inorder-timing.py f348cf78072c tests/configs/memtest-ruby.py f348cf78072c tests/configs/memtest.py f348cf78072c tests/configs/o3-timing-mp.py f348cf78072c tests/configs/o3-timing.py f348cf78072c tests/configs/rubytest-ruby.py f348cf78072c tests/configs/simple-atomic-mp.py f348cf78072c tests/configs/simple-atomic.py f348cf78072c tests/configs/simple-timing-mp-ruby.py f348cf78072c tests/configs/simple-timing-mp.py f348cf78072c tests/configs/simple-timing-ruby.py f348cf78072c tests/configs/simple-timing.py f348cf78072c Diff: http://reviews.m5sim.org/r/943/diff Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
