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(Updated Aug. 7, 2012, 12:35 p.m.) Review request for Default. Description (updated) ------- Changeset 9147:f08293f9d49e --------------------------- ARM: fix miscreg ctr that causes panic with checker this patch fixes the miscreg ctr code so that it no longer panics when using the checker. it also sets all fields other than the format field to 0 if there are no caches. the checker cpu getInst/DataPort() functions are changed so that they no longer panic. instead, there is a warn() emphasizing the fact that ports don't really have neighbors that belong to the checker. Diffs (updated) ----- src/arch/arm/isa.cc a61fdbbc1d45572c4a6af890372cbbaf3a23c68d src/cpu/checker/cpu.hh a61fdbbc1d45572c4a6af890372cbbaf3a23c68d Diff: http://reviews.gem5.org/r/1344/diff/ Testing ------- Thanks, Anthony Gutierrez _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
