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src/arch/arm/isa.cc <http://reviews.gem5.org/r/1344/#comment3372> I really think we should avoid doing anything along these lines and instead take the plunge and to the CPU -> core switch and then introduce the CPU "box" simobject that is merely a hierarchy with pointers to caches etc. I really do not like to have assumptions on the connectivity. If we could insert a monitor for example then this code would break. Also, does this work with switching CPUs where the instport won't be connected to start with? Checkers etc? src/cpu/checker/cpu.hh <http://reviews.gem5.org/r/1344/#comment3373> How bad would it be to make the CheckerCPU inherit from something other than a BaseCPU, or insert another class in the hierarchy for "real" CPU vs CPU-like behaviour (the checker)? It seems we try to squeeze a square peg in a round hole here... and also with some other issues related to the checker. - Andreas Hansson On Aug. 7, 2012, 12:35 p.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1344/ > ----------------------------------------------------------- > > (Updated Aug. 7, 2012, 12:35 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9147:f08293f9d49e > --------------------------- > ARM: fix miscreg ctr that causes panic with checker > > this patch fixes the miscreg ctr code so that it no longer panics > when using the checker. it also sets all fields other than the > format field to 0 if there are no caches. > > the checker cpu getInst/DataPort() functions are changed so that > they no longer panic. instead, there is a warn() emphasizing the > fact that ports don't really have neighbors that belong to the > checker. > > > Diffs > ----- > > src/arch/arm/isa.cc a61fdbbc1d45572c4a6af890372cbbaf3a23c68d > src/cpu/checker/cpu.hh a61fdbbc1d45572c4a6af890372cbbaf3a23c68d > > Diff: http://reviews.gem5.org/r/1344/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
