> On Aug. 9, 2012, 2:12 p.m., Andreas Hansson wrote: > > src/arch/arm/isa.cc, line 226 > > <http://reviews.gem5.org/r/1344/diff/2/?file=28607#file28607line226> > > > > I really think we should avoid doing anything along these lines and > > instead take the plunge and to the CPU -> core switch and then introduce > > the CPU "box" simobject that is merely a hierarchy with pointers to caches > > etc. > > > > I really do not like to have assumptions on the connectivity. If we > > could insert a monitor for example then this code would break. Also, does > > this work with switching CPUs where the instport won't be connected to > > start with? Checkers etc? > > Geoffrey Blake wrote: > Maybe I'm missing something here, but would it not be better to attempt > setting this register at config time with the python code in the same way > that the device model registers are handled and have it as a param that is > passed to a CPU constructor? > > Andreas Hansson wrote: > I think that sounds like a good idea. I don't know all the details, I am > merely keen to arrive at a solution that does not contain a lot of hidden > assumptions.
The question is how to do it. If you use parent.any it will fail when a the system doesn't have a cache. Otherwise changes to the config files are needed. Maybe teh best thing to do is default it to 64 bytes and allow the parameter to be set , and change the config files appropriately. While i'd like to see the cpu container objects, that is going to take a while and we need to get the checker regression going sooner then that. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1344/#review3255 ----------------------------------------------------------- On Aug. 7, 2012, 12:35 p.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1344/ > ----------------------------------------------------------- > > (Updated Aug. 7, 2012, 12:35 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9147:f08293f9d49e > --------------------------- > ARM: fix miscreg ctr that causes panic with checker > > this patch fixes the miscreg ctr code so that it no longer panics > when using the checker. it also sets all fields other than the > format field to 0 if there are no caches. > > the checker cpu getInst/DataPort() functions are changed so that > they no longer panic. instead, there is a warn() emphasizing the > fact that ports don't really have neighbors that belong to the > checker. > > > Diffs > ----- > > src/arch/arm/isa.cc a61fdbbc1d45572c4a6af890372cbbaf3a23c68d > src/cpu/checker/cpu.hh a61fdbbc1d45572c4a6af890372cbbaf3a23c68d > > Diff: http://reviews.gem5.org/r/1344/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
