> On Aug. 9, 2012, 2:12 p.m., Andreas Hansson wrote: > > src/cpu/checker/cpu.hh, line 122 > > <http://reviews.gem5.org/r/1344/diff/2/?file=28608#file28608line122> > > > > How bad would it be to make the CheckerCPU inherit from something other > > than a BaseCPU, or insert another class in the hierarchy for "real" CPU vs > > CPU-like behaviour (the checker)? > > > > It seems we try to squeeze a square peg in a round hole here... and > > also with some other issues related to the checker. > > Geoffrey Blake wrote: > I think there are a few areas where instructions pass their > ThreadContexts to some component that then expects to get a BaseCPU ptr to > set some state that might make this more difficult than expected. A quick > search shows the TLBs for ARM expect this behavior. But, it might be good to > separate the checker further away from the CPU classes just to avoid any > confusion. > > Andreas Hansson wrote: > You're the expert Geoff :) > > Conceptually I think we should do something along these lines, but where > exactly to make the cut I don't know. Do you have an idea of how much work it > would be?
I don't have the bandwidth to volunteer attempting to make the changes is my main objection right now. =) I think the separation has already been made in the majority of the code that directly interacts with the checker, asking for a CheckerCpuPtr instead of CpuPtr now. Its the hidden areas I'm not terribly familiar with where I don't have a good grasp of the difficulty to making such changes. I.e. components that interact mainly through ThreadContext's which include the instructions, TLBs, architecture specific handlers etc. What other problems were happening with the Checker to push removing the Checker from inheriting from BaseCPU? I haven't been following close enough obviously? - Geoffrey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1344/#review3255 ----------------------------------------------------------- On Aug. 7, 2012, 12:35 p.m., Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1344/ > ----------------------------------------------------------- > > (Updated Aug. 7, 2012, 12:35 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9147:f08293f9d49e > --------------------------- > ARM: fix miscreg ctr that causes panic with checker > > this patch fixes the miscreg ctr code so that it no longer panics > when using the checker. it also sets all fields other than the > format field to 0 if there are no caches. > > the checker cpu getInst/DataPort() functions are changed so that > they no longer panic. instead, there is a warn() emphasizing the > fact that ports don't really have neighbors that belong to the > checker. > > > Diffs > ----- > > src/arch/arm/isa.cc a61fdbbc1d45572c4a6af890372cbbaf3a23c68d > src/cpu/checker/cpu.hh a61fdbbc1d45572c4a6af890372cbbaf3a23c68d > > Diff: http://reviews.gem5.org/r/1344/diff/ > > > Testing > ------- > > > Thanks, > > Anthony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
