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(Updated Sept. 1, 2012, 10:12 a.m.) Review request for Default. Description (updated) ------- Changeset 9182:3377bf0ff708 --------------------------- ARM: don't set cache fields of CTR reg if there are no caches currently the CTR reg sets its fields based on the block size of the peer connected to its inst port. in the cache where there are no caches it doesn't make sense to do so. this patch sets only the relevant fields of the CTR reg if there are no caches and leaves the cache-related fields as 0. Diffs (updated) ----- src/arch/arm/isa.cc 42807286d6cbaa33b43942d7d15ec34cd5dd5d1d Diff: http://reviews.gem5.org/r/1344/diff/ Testing ------- Thanks, Anthony Gutierrez _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
