-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/1667/#review4735
-----------------------------------------------------------
One additional issue:
Somehow the unproxying of the eventq_index does not work for the PC regressions
due to some odd circular relationship. The change below is needed for it to
work again.
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -57,10 +57,9 @@
behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
# Serial port and terminal
- terminal = Terminal()
com_1 = Uart8250()
com_1.pio_addr = x86IOAddress(0x3f8)
- com_1.terminal = terminal
+ com_1.terminal = Terminal()
# Devices to catch access to non-existant serial ports.
fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8)
- Andreas Hansson
On Sept. 21, 2013, 6:36 p.m., Nilay Vaish wrote:
>
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1667/
> -----------------------------------------------------------
>
> (Updated Sept. 21, 2013, 6:36 p.m.)
>
>
> Review request for Default.
>
>
> Repository: gem5
>
>
> Description
> -------
>
> Changeset 9885:ab020183761b
> ---------------------------
> sim: simulate with multiple event queues
> This patch extends the patch Steve posted on the reviewboard (846). The patch
> updated with all the changes that have taken place over last 15 months. Code
> has been added so as actually carry out a quantum-based parallel simulation.
>
> The patch was tested in two different configurations:
> 1. ruby_network_test.py: in this simulation L1 cache controllers receive
> requests from the cpu. The requests are replied to immediately without
> any communication taking place with any other level.
> 2. twosys-tsunami-simple-atomic: this configuration simulates a client-server
> system which are connected by an ethernet link.
>
> We still lack the ability to communicate using message buffers or ports. But
> other things like simulation start and end, synchronizing after every quantum
> seem to be working.
>
>
> Diffs
> -----
>
> src/SConscript 372d3611c693
> src/base/barrier.hh PRE-CREATION
> src/cpu/base.cc 372d3611c693
> src/dev/etherlink.cc 372d3611c693
> src/python/m5/SimObject.py 372d3611c693
> src/python/m5/event.py 372d3611c693
> src/python/m5/main.py 372d3611c693
> src/python/m5/simulate.py 372d3611c693
> src/python/swig/event.i 372d3611c693
> src/sim/Root.py 372d3611c693
> src/sim/SConscript 372d3611c693
> src/sim/core.hh 372d3611c693
> src/sim/core.cc 372d3611c693
> src/sim/debug.cc 372d3611c693
> src/sim/eventq.hh 372d3611c693
> src/sim/eventq.cc 372d3611c693
> src/sim/eventq_impl.hh 372d3611c693
> src/sim/global_event.hh PRE-CREATION
> src/sim/global_event.cc PRE-CREATION
> src/sim/root.cc 372d3611c693
> src/sim/serialize.hh 372d3611c693
> src/sim/serialize.cc 372d3611c693
> src/sim/sim_events.hh 372d3611c693
> src/sim/sim_events.cc 372d3611c693
> src/sim/sim_exit.hh 372d3611c693
> src/sim/sim_object.cc 372d3611c693
> src/sim/simulate.hh 372d3611c693
> src/sim/simulate.cc 372d3611c693
> src/sim/stat_control.cc 372d3611c693
>
> Diff: http://reviews.gem5.org/r/1667/diff/
>
>
> Testing
> -------
>
>
> Thanks,
>
> Nilay Vaish
>
>
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
