In x86 it looks like I made prefetches literally the same microop as regular loads but with the extra Request flags set. I don't know why O3 is the way it is, but it seems important to figure out before changing anything. I don't have any opposition off hand.
Gabe Ali Saidi wrote: > Looking at the timing and o3 cpu, for prefetch instructions the CPUs do > nothing (they generate an EA, but do nohting with it) and there isn't an > initiateAcc() completeAcc() method generated for the instructions for > Alpha. Anyone know why? Anyone opposed to changing these to execute > similar to a real load but not allow them to cause a fault? > > Thanks, > Ali > > > > > On Sun, 03 Oct 2010 02:19:56 -0000, "Ali Saidi" <[email protected]> > wrote: > >> ----------------------------------------------------------- >> This is an automatically generated e-mail. To reply, visit: >> http://reviews.m5sim.org/r/256/#review362 >> ----------------------------------------------------------- >> >> >> >> src/cpu/simple/timing.cc >> <http://reviews.m5sim.org/r/256/#comment479> >> >> This change marks prefetches as regular load ops so they can >> actually execute. Alpha prefetches don't do anything at the moment and >> don't have an initiateAcc() method, so there needs to be a change to >> the ISA description for them. >> >> >> - Ali >> >> >> On 2010-10-02 19:19:53, Ali Saidi wrote: >> >>> ----------------------------------------------------------- >>> This is an automatically generated e-mail. To reply, visit: >>> http://reviews.m5sim.org/r/256/ >>> ----------------------------------------------------------- >>> >>> (Updated 2010-10-02 19:19:53) >>> >>> >>> Review request for Default. >>> >>> >>> Summary >>> ------- >>> >>> ARM: Mark prefetches as such and allow timing CPU to handle them. >>> >>> >>> Diffs >>> ----- >>> >>> src/arch/arm/faults.cc e78b6bba67ca >>> src/arch/arm/isa/insts/ldr.isa e78b6bba67ca >>> src/cpu/simple/timing.cc e78b6bba67ca >>> >>> Diff: http://reviews.m5sim.org/r/256/diff >>> >>> >>> Testing >>> ------- >>> >>> >>> Thanks, >>> >>> Ali >>> >>> >>> >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
