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src/cpu/simple/timing.cc <http://reviews.m5sim.org/r/256/#comment480> I don't think this is right. This will likely break X86_FS where curMacroStaticInst will almost always be set. If you're having trouble with this in ARM, a possible culprit is that you're not setting isDelayedCommit on microops that aren't at the end of a macroop. src/cpu/simple/timing.cc <http://reviews.m5sim.org/r/256/#comment482> Prefetch faults should ideally be surpressed at their source, not here. At the source we already implicitly know the instruction shouldn't fault. Here, we have to rediscover that all the time. src/cpu/simple/timing.cc <http://reviews.m5sim.org/r/256/#comment481> I'm not sure this is necessary. If the CPU isn't running, that's because it's waiting for something. If it's waiting for something, then it's doing a memory access, and there won't be a fault. The original assert should be right. - Gabe On 2010-10-02 19:19:53, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/256/ > ----------------------------------------------------------- > > (Updated 2010-10-02 19:19:53) > > > Review request for Default. > > > Summary > ------- > > ARM: Mark prefetches as such and allow timing CPU to handle them. > > > Diffs > ----- > > src/arch/arm/faults.cc e78b6bba67ca > src/arch/arm/isa/insts/ldr.isa e78b6bba67ca > src/cpu/simple/timing.cc e78b6bba67ca > > Diff: http://reviews.m5sim.org/r/256/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
