> On 2010-10-09 13:38:40, Gabe Black wrote: > > src/cpu/simple/timing.cc, line 765 > > <http://reviews.m5sim.org/r/256/diff/1/?file=3666#file3666line765> > > > > Prefetch faults should ideally be surpressed at their source, not here. > > At the source we already implicitly know the instruction shouldn't fault. > > Here, we have to rediscover that all the time.
I don't agree. If you suppress this at the source the CPU model doesn't know if it should actually try and issue the instruction, so that would have to be checked some how. Additionally, in most cases there is one or two place in the TLB that a correct translation is returned and as many places where a fault is returned. Checking there would complication all of the code paths. > On 2010-10-09 13:38:40, Gabe Black wrote: > > src/cpu/simple/timing.cc, line 712 > > <http://reviews.m5sim.org/r/256/diff/1/?file=3666#file3666line712> > > > > I don't think this is right. This will likely break X86_FS where > > curMacroStaticInst will almost always be set. If you're having trouble with > > this in ARM, a possible culprit is that you're not setting isDelayedCommit > > on microops that aren't at the end of a macroop. I'll look at isDelayedCommit. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/256/#review364 ----------------------------------------------------------- On 2010-10-02 19:19:53, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/256/ > ----------------------------------------------------------- > > (Updated 2010-10-02 19:19:53) > > > Review request for Default. > > > Summary > ------- > > ARM: Mark prefetches as such and allow timing CPU to handle them. > > > Diffs > ----- > > src/arch/arm/faults.cc e78b6bba67ca > src/arch/arm/isa/insts/ldr.isa e78b6bba67ca > src/cpu/simple/timing.cc e78b6bba67ca > > Diff: http://reviews.m5sim.org/r/256/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
