On Sun, 25 Nov 2012, Pavlos Maniotis wrote:
For anyone who would like to share one L1 cache among multiple cpus I
have found a possible solution that seems to work:
1) I modified the ruby protocol specific python config file (for example
MOESI_CMP_direcory.py in /gem5/configs/ruby) to create just one L1
cache, one controller and one sequencer
2) In ruby_fs.py I connected each cpu's cache ports to the one L1 ruby
sequencer created in step 1
In this way I successfully simulated fft splash2 benchmark in ALPHA fs
mode.
I am not convinced that the simulator works correctly without modifying
the protocol itself. You might want to post your changes to the mailing
list.
--
Nilay
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