Hi Pavlos, There have been numerous discussions around the CPU to L1 bandwidth/latency, and by default it is not limited (i.e. it is just two ports connected together). IF you want (and as Steve has previously pointed out) you can insert a CoherentBus between the CPU and L1 if you want, but you will have to change the config scripts.
Good luck. Andreas On 23/11/2012 14:34, "Pavlos Maniotis" <[email protected]> wrote: >Hi Andreas, > >Thanks for the info, does it also apply for the Classic Memory System? >I was thinking that there was a bus between CPU and L1 with some width >and some frequency, for example 64bit and 2GHz. I wanted to test two >different systems and compare the performance between them: > >1) CPU (2GHz) <--------[bus 64 width, 2GHz]---------> L1 (2GHz) ->to L2 >2) CPU (2GHz) <--------[bus 32 width, 4GHz]---------> L1 (4GHz) ->to L2 > >Do you think that I cannot use gem5 to do this experiment? > >Thanks again, >Pavlos >On Fri, 2012-11-23 at 14:14 +0000, Andreas Hansson wrote: >> Hi Pavlos, >> >> There is no bus between the CPU core and the L1, just a "port" >>connection. >> The PIO bus is only used for PIO, and should not have a great impact on >> your benchmark unless it is very I/O intensive. >> >> Andreas >> >> On 23/11/2012 12:29, "Pavlos Maniotis" <[email protected]> wrote: >> >> >Hello everyone, >> > >> >I use ruby (MOESI_CMP_directory) and I want to simulate a system >> >with one CPU (frequency=2GHz) and L1 and L2 caches (frequency=4GHz). >> >I also want the bus between cpu and cache >> >to run at 4GHz with width 32 bits. So I have to set the cpu >> >frequency equal to 4GHz (ruby_fs.py -> CPUClass.clock = '2GHz') >> >and ruby frequency equal to 2GHz >> >(Ruby.py -> system.ruby = RubySystem(clock = 4, >> > stats_filename = options.ruby_stats, >> > no_mem_vec = options.use_map)). >> > >> >I suppose these changes are right, my main concern is: >> > >> >Do I have to change system.piobus frequency >> >to 4GHz and width to 4 bytes (file FSConfig.py, function >> >makeLinuxAlphaRubySystem)? >> >Is this the bus between cpu and L1 cache? If it is not >> >how can I configure the bus between L1 and CPU? >> > >> >I am little bit confused about the interconnection system. >> > >> >Thanks in advance for any help, >> >Pavlos >> > >> > >> >_______________________________________________ >> >gem5-users mailing list >> >[email protected] >> >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > >> >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >>confidential and may also be privileged. If you are not the intended >>recipient, please notify the sender immediately and do not disclose the >>contents to any other person, use it for any purpose, or store or copy >>the information in any medium. Thank you. >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > >_______________________________________________ >gem5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
